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參數(shù)資料
| 型號(hào)： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 129K |
| 代理商： | Z684 |
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I
Z684 PCI Bus Controller
I
11
OKI SEMICONDUCTOR
Z684 PCI Mega Macrocell
The Z684 functions as a bus protocol translator. The Z684 translates i486-like module bus signals into PCI
bus signals. The two four-entry FIFOs are used to improve write transactions performance. The Z684 is
partitioned into the following blocks:
Configuration registers
FIFO control logic
Post-write FIFOs
Master, slave and parity blocks
The following subsection describe these blocks in turn.
Configuration Registers
There are 64 byte-wide configuration registers implemented in the Z684 to support configuration control
of the PCI device. The configuration registers can either be accessed from the module bus internally or
from the PCI bus externally.
FIFO Control Logic
FIFO control provides the data traffic handling and scheduling of the Z684. It arranges priority of the data
flow when multiple transactions occur.
Post-Write FIFOs
All write cycles are postable. Two 4x36-bit FIFOs store the address, data, and command/ byte enable
information during write transactions.
The module-to-PCI write FIFO (“MPWR FIFO”) stores data and byte enable bits during module-to-
PCI memory write cycles (single or burst).
The PCI-to-module write FIFO (“PMWR FIFO”) stores address, data and command/ byte enable
bits during PCI-to-module cycles (single or burst).
The FIFOs eliminate wait states in most write transaction and thus improve system performance.
Figure 207
on the following page shows the data path from the Customer Application Module to the PCI
bus.
During module-to-PCI memory write cycles, the data and byte-enable bits are stored in the MPWR FIFO.
Only four 36-bit data words can be stored in the FIFO. If a burst-write transaction fills up the FIFO, the
Z684 issues a retry request by asserting PBOFFB LOW. The transaction then resumes when the FIFO is
not full.
A request to access the PCI bus is sent whenever MPWR FIFO is not empty. The data and byte-enable bits
are then retired to the PCI memory address of a specific agent.
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| Z706LR | Automotive Fuse; Current Rating:20A; Voltage Rating:32V; Fuse Type:Fast Acting; Fuse Terminals:Blade; Length:18.54mm; Series:257; Fuse Size/Group:18.54 x 19.05 x 5.08mm |
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