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參數(shù)資料
| 型號： | Z684 |
| 英文描述： | FUSE 3A/125V SUB-MINIATURE PICO |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大小： | 129K |
| 代理商： | Z684 |
I
Z684 PCI Bus Controller
I
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
12
OKI SEMICONDUCTOR
The FIFO can be disabled by programming the FIFO enable bit, bit 0, in the Z684 Control Register. The
data and byte-enable bits pass through the data and byte enable latches when the FIFO is disabled.
Figure 208
shows the data path of a PCI device write to module memory.
During PCI-to-module memory write cycles, the address, data and command/ byte-enable bits are stored
in the PMWR FIFO. As with the MPWR FIFO, only four 36-bit address, data and command/ byte-enable
entries can be stored in the FIFO. If a PCI burst-write transaction fills up the FIFO, the Z684 issues a retry
request by asserting OSTOPB and ESTOPB LOW. The transaction then resumes when the FIFO is not full.
A request to access the Customer Application Module bus is sent whenever the MPWR FIFO is not empty.
The data and byte-enable bits are then retired to the Customer Application Module memory specified by
the address.
As with the MPWR FIFO, the PMWR FIFO can be disabled by programming the same FIFO enable bit 0
in the Z684 Control Register. The address/ data and command/ byte enable bits pass through the PMAD
and PMBE latches when the PMWR FIFO is disabled.
OAD[31:0]
32
PAD
Latch
MCLK
M
M
OCBEB[3:0]
4
PBE
Latch
M
MPADRS
Latch
Latch
MPDATA
4 x 36
MPWR FIFO
MPBE
Latch
32
32
4
MCLK
MA[31:0]
MD[31:0]
MBEB[3:0]
Figure 207. Data Path from the Customer Application Module to the PCI Bus
IAD[31:0]
32
PMAD
Latch
ICBEB[3:0]
4
PMBE
Latch
M
MA
Latch
MD
Latch
4 x 36
PMWR FIFO
MBE
Latch
32
4
PA[31:0]
PD[31:0]
PBEB[3:0]
MCLK
M
32
MCLK
MCLK
M
Figure 208. Data Path from the PCI Bus to the Customer Application Module
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