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參數資料
型號: 70V659S15DR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 128K X 36 DUAL-PORT SRAM, 15 ns, PQFP208
封裝: 28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208
文件頁數: 1/24頁
文件大小: 316K
代理商: 70V659S15DR
2004 Integrated Device Technology, Inc.
1
MARCH 2004
DSC-4869/5
CE0R
R/
WR
CE1R
BE0R
BE1R
BE2R
BE3R
128/64/32K x 36
MEMORY
ARRAY
Address
Decoder
A16R(1)
A0R
Address
Decoder
CE0L
R/
WL
CE1L
BE0L
BE1L
BE2L
BE3L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
B
E
3
R
B
E
2
R
B
E
1
R
B
E
0
R
I/O0L- I/O35L
A16 L(1)
A0L
I/O0R -I/O35R
Di n_L
ADDR_L
Di n_R
ADDR_R
OER
OEL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEML
INTL(3)
BUSYL(2,3)
M/
S
R/
WL
OEL
R/
WR
OER
CE0L
CE1L
CE0R
CE1R
BUSYR(2,3)
SEMR
INTR(3)
TMS
TCK
TRST
TDI
TDO
JTAG
4869 drw 01
Functional Block Diagram
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
HIGH-SPEED 3.3V
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
IDT70V659/58/57S
1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
NOTES:
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相關代理商/技術參數
參數描述
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70V7319S133BC8 功能描述:IC SRAM 4.5MBIT 133MHZ 256CABGA 制造商:idt, integrated device technology inc 系列:- 包裝:帶卷(TR) 零件狀態:有效 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口,同步 存儲容量:4.5M(256K x 18) 速度:133MHz 接口:并聯 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:0°C ~ 70°C(TA) 封裝/外殼:256-LBGA 供應商器件封裝:256-CABGA(17x17) 標準包裝:1,000
70V7319S133BF 功能描述:靜態隨機存取存儲器 RoHS:否 制造商:IDT 存儲容量: 組織: 訪問時間: 電源電壓-最大: 電源電壓-最小: 最大工作電流: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝:
70V7319S133BF8 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 15NS/4.2NS 208FBGA - Tape and Reel
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