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參數資料
| 型號： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁數： | 107/144頁 |
| 文件大小： | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
65
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
9.4.2
X-PORT CONFIGURED AS INPUT
If data input mode is selected at the expansion port, then
the scaler can choose it’s input data stream from the
on-chip video decoder, or from expansion port (controlled
by bit SCSRC[1:0]91H[5:4]). Byte serial YUV 4:2:2, or
subsets for other sampling schemes, or raw samples from
an external ADC may be input (see also bits
FSC[2:0]91H[2:0]). The input stream must be
accompanied by an external clock XCLK, qualifier XDQ
and reference signals XRH and XRV. Instead of the
reference signal, embedded SAV and EAV codes
according to ITU 656 are also accepted. The protection
bits are not evaluated.
XRH and XRV carry the horizontal and vertical
synchronization signals for the digital video stream
through the expansion port. The field ID of the input video
stream is carried in the phase (edge) of XRV and state of
XRH, or directly as FS (frame sync, odd/even signal) on
the XRV pin (controlled by XFDV[92H[7]],
XFDH[92H[6]] and XDV1[92H[5]]).
The trigger events on XRH (rising/falling edge) and XRV
(rising/falling/both edges) for the scalers acquisition
window are defined by XDV[1:0]92H[5:4] and
XDH[92H[2]]. Also the signal polarity of the qualifier can be
defined (bit XDQ[92H[1]]). Alternatively to a qualifier, the
input clock can be applied to a gated clock (means clock
gated with a data qualifier, controlled by bit
XCKS[92H[0]]). In this event, all input data will be qualified.
9.5
Image port (I-port)
The image port transfers data from the scaler as well as
from the VBI-data slicer, if so selected (maximum
33 MHz). The reference clock is available at the ICLK pin,
as output, or as input (maximum 33 MHz). As output, ICLK
is derived from the locked decoder or expansion port input
clock. The data stream from the scaler output is normally
discontinuous. Therefore valid data during a clock cycle is
accompanied by a data qualifying (data valid) flag on
pin IDQ. For pin constrained applications the IDQ pin can
be programmed to function as gated clock output (bit
ICKS2[80H[2]]).
The data formats at the image port are defined in Dwords
of 32 bits (4 bytes), like the related FIFO structures. But
the physical data stream at the image port is only 16-bit or
8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are
used for chrominance data. The four bytes of the Dwords
are serialized in words or bytes.
Available formats are:
YUV4:2:2,
YUV4:1:1,
Raw samples
Decoded VBI-data.
For handshake with the receiving VGA controller, or other
memory or bus interface circuitry, F, H and V reference
signals and programmable FIFO flags are provided. The
information will be provided on pins IGP0, IGP1, IGPH and
IGPV. The functionality on this pins is controlled via
subaddresses 84H and 85H.
VBI-data is collected over an entire line in its own FIFO,
and transferred as an uninterrupted block of bytes.
Decoded VBI-data can be signed by the VBI flag on
pin IGP0/1.
As scaled video data and decoded VBI-data may come
from different and asynchronous sources, an arbitration
scheme is needed. Normally VBI-data slicer has priority.
The image port consists of the pins and/or signals, as
listed in Table 31.
For pin constrained applications, or interfaces, the relevant
timing and data reference signals can also get encoded
into the data stream. Therefore the corresponding pins do
not need to get connected. The minimum image port
configuration requires 9 pins only, i.e. 8 pins for data
including codes, and 1 pin for clock or gated clock. The
inserted codes are defined in close relation to the
ITU/CCIR-656 (D1) recommendation, where possible.
The following deviations from
“ITU 656 recommendation”
are implemented at SAA7114H’s image port interface:
SAV and EAV codes are only present in those lines,
where data is to be transferred, i.e. active video lines, or
VBI-raw samples, no codes for empty lines
There may be more or less than 720 pixels between
SAV and EAV
Data content and number of clock cycles during
horizontal and vertical blanking is undefined, and may
be not constant
Data stream may be interleaved with not-valid data
codes, 00H, but SAV and EAV 4-byte codes are not
interleaved with not-valid data codes
There may be an irregular pattern of not-valid data, or
IDQ, and as a result, ‘CB -Y-CR - Y -’ is not in a fixed
phase to a regular clock divider
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