
2000
Mar
15
84
Philips
Semiconductors
Preliminar
y
specication
P
AL/NTSC/SECAM
video
decoder
with
adaptiv
e
P
AL/NTSC
comb
lter
,VBI-data
slicer
and
high
perf
or
mance
scaler
SAA7114H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Header and data identication
(DID) code control
5D
FVREF
(1)
DID5
DID4
DID3
DID2
DID1
DID0
Sliced data identication (SDID)
code
5E
(1)
SDID5
SDID4
SDID3
SDID2
SDID1
SDID0
Reserved
5F
(1)
Slicer status byte 0 (read only)
60
FC8V
FC7V
VPSV
PPV
CCV
Slicer status byte 1 (read only)
61
F21_N
LN8
LN7
LN6
LN5
LN4
Slicer status byte 2 (read only)
62
LN3
LN2
LN1
LN0
DT3
DT2
DT1
DT0
Reserved
63 to 7F
(1)
X-port, I-port and the scaler part: registers 80H to EFH
TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH
Global control 1
80
(1)
SMOD
TEB
TEA
ICKS3
ICKS2
ICKS1
ICKS0
Reserved
81 and
82
(1)
X-port I/O enable and output
clock phase control
83
(1)
XPCK1
XPCK0
(1)
XRQT
XPE1
XPE0
I-port signal denitions
84
IDG01
IDG00
IDG11
IDG10
IDV1
IDV0
IDH1
IDH0
I-port signal polarities
85
ISWP1
ISWP0
ILLV
IG0P
IG1P
IRVP
IRHP
IDQP
I-port FIFO ag control and
arbitration
86
VITX1
VITX0
IDG02
IDG12
FFL1
FFL0
FEL1
FEL0
I-port I/O enable, output clock
and gated clock phase control
87
IPCK3
IPCK2
IPCK1
IPCK0
(1)
IPE1
IPE0
Power save control
88
CH4EN
CH2EN
SWRST
DPROG
SLM3
(1)
SLM1
SLM0
Reserved
89 to 8E
(1)
Status information scaler part
8F
XTRI
ITRI
FFIL
FFOV
PRDON
ERR_OF
FIDSCI
FIDSCO
TASK A DEFINITION: REGISTERS 90H TO BFH
Basic settings and acquisition window denition
Task handling control
90
CONLH
OFIDC
FSKP2
FSKP1
FSKP0
RPTSK
STRC1
STRC0
X-port formats and conguration
91
CONLV
HLDFV
SCSRC1
SCSRC0
SCRQE
FSC2
FSC1
FSC0
X-port input reference signal
denition
92
XFDV
XFDH
XDV1
XDV0
XCODE
XDH
XDQ
XCKS
REGISTER FUNCTION
SUB
ADDR.
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0