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參數(shù)資料
| 型號(hào)： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁數(shù)： | 87/144頁 |
| 文件大小： | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
47
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
8.3.2.2
Horizontal ne scaling (variable phase delay
lter; subaddresses A8H to AFH and
D8H to DFH)
The horizontal fine scaling (VPD) should operate at scaling
ratios between 1
2 and 2 (0.8 and 1.6), but can also be
used for direct scale in the range from 1
7.999 to (theoretical)
zoom 3.5 (restriction due to the internal data path
architecture), without prescaler.
In combination with the prescaler a compromise between
sharpness impression and alias can be found, which is
signal source and application dependent.
For the luminance channel a filter structure with 10 taps is
implemented, for the chrominance a filter with 4 taps.
Luminance and chrominance scale increments
(XSCY[12:0]A9H[4:0]A8H[7:0] and
XSCC[12:0]ADH[4:0]ACH[7:0]) are defined
independently, but must be set in a 2 : 1 relation in the
actual data path implementation. The phase offsets
XPHY[7:0]AAH[7:0] and XPHC[7:0]AEH[7:0] can be used
to shift the sample phases slightly. XPHY[7:0] and
XPHC[7:0] covers the phase offset range 7.999T to 1
32T.
The phase offsets should also be programmed in a 2 : 1
ratio.
The underlying phase controlling DTO has a 13-bit
resolution.
According to the equations
and
the VPD covers the scale
range from 0.125 to zoom 3.5. VPD acts equivalent to a
polyphase filter with 64 possible phases. In combination
with the prescaler, it is possible to get very accurate
samples from a highly anti-aliased integer down-scaled
input picture.
8.3.3
VERTICAL SCALING
The vertical scaler of the SAA7114H consists of a line
FIFO buffer for line repetition and the vertical scaler block,
which implements the vertical scaling on the input data
stream in 2 different operational modes from theoretical
zoom by 64 down to icon size 1
64. The vertical scaler is
located between the BCS and horizontal fine scaler, so
that the BCS can be used to compensate the DC gain
amplification of the ACM mode (see Section 8.3.3.2) as
the internal RAMs are only 8-bit wide.
8.3.3.1
Line FIFO buffer (subaddresses 91H, B4H and
C1H, E4H)
The line FIFO buffer is a dual ported RAM structure for
768 pixels, with asynchronous write and read access. The
line buffer can be used for various functions, but not all
functions may be available simultaneously.
The line buffer can buffer a complete unscaled active video
line or more than one shorter lines (only for non-mirror
mode), for selective repetition for vertical zoom-up.
For zooming up 240 lines to 288 lines e.g., every fourth
line is requested (read) twice from the vertical scaling
circuitry for calculation.
For conversion of a 4 : 2 : 0 or 4:1:0 input sampling
scheme (MPEG, video phone, video YUV-9) to CCIR like
sampling scheme 4:2:2, the chrominance line buffer is
read twice of four times, before being refilled again by the
source. By means of the input acquisition window
definition it has to be preserved, that the processing starts
with a line containing luminance and chrominance
information for 4:2:0 and 4:1:0 input. The bits
FSC[2:1]91H[2:1] are defining the distance between the
Y/C lines. In case of 4 :2:2 and 4 : 1 : 1 FSC2 to FSC1
have to be set to ‘00’.
The line buffer can also be used for mirroring, i.e. for
flipping the image left to right, for the vanity picture in video
phone application (bit YMIR[B4H[4]]). In mirror mode only
one active prescaled line can be held in the FIFO at a time.
The line buffer can be utilized as excessive pipeline buffer
for discontinuous and variable rate transfer conditions at
expansion port or image port.
XSCY[12:0]
1024
Npix_in
XPSC
--------------------
×
1
Npix_out
-----------------------
×
=
XSCC[12:0]
XSCY[12:0]
2
-------------------------------
=
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