
2000 Mar 15
116
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Table 94 Power save control; global set 88H[7:4]
Notes
1. X = don’t care.
2. Bit SWRST is now located here.
15.5.4
SUBADDRESS 8FH (READ-ONLY REGISTER)
Table 95 Status information scaler part; 8FH[7:0]
Note
1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read.
POWER SAVE CONTROL
CONTROL BITS D7 TO D4(1)
CH4EN
CH2EN
SWRST(2)
DPROG
DPROG = 0 after reset
X
0
DPROG = 1 can be used to assign that the device has been
programmed; this bit can be monitored in the scalers status byte,
bit PRDON; if DPROG was set to logic 1 and PRDON status bit
shows a logic 0 a power- or start-up fail has occurred
XXX
1
Scaler path is reset to it’s idle state, software reset
X
0
X
Scaler is switched back to operation
X
1
X
AD1x analog channel is in power-down mode
X
0
X
AD1x analog channel is active
X
1
X
AD2x analog channel is in power-down mode
0
X
AD2x analog channel is active
1
X
BIT
I2C-BUS
STATUS BIT
FUNCTION(1)
D7
XTRI
status on input pin XTRI, if not used for 3-state control, usable as hardware ag for software use
D6
ITRI
status on input pin ITRI, if not used for 3-state control, usable as hardware ag for software use
D5
FFIL
status of the internal ‘FIFO almost lled’ ag
D4
FFOV
status of the internal ‘FIFO overow’ ag
D3
PRDON
copy of bit DPROG, can be used to detect power-up and start-up fails
D2
ERR_OF
error ag of scalers output formatter, normally set, if the output processing needs to be
interrupted, due to input/output data rate conicts, e.g. if output data rate is much too low and all
internal FIFO capacity used
D1
FIDSCI
status of the eld sequence ID at the scalers input
D0
FIDSCO
status of the eld sequence ID at the scalers output, scaler processing dependent