
2000 Mar 15
110
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
15.4.9
SUBADDRESS 60H (READ-ONLY REGISTER)
Table 78 Slicer status byte 0; 60H[6:2]
15.4.10 SUBADDRESSES 61H AND 62H (READ-ONLY REGISTERS)
Table 79 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]
15.5
Programming register interfaces and scaler part
15.5.1
SUBADDRESS 80H
Table 80 Global control 1; global set 80H[3:0]
X = don’t care.
Note
1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1.
BIT
DESCRIPTION
SYMBOL VALUE
FUNCTION
D6
framing code valid
FC8V
0
no framing code (0 error) in the last frame detected
1
framing code with 0 error detected
D5
framing code valid
FC7V
0
no framing code (1 error) in the last frame detected
1
framing code with 1 error detected
D4
VPS valid
VPSV
0
no VPS in the last frame
1
VPS detected
D3
PALplus valid
PPV
0
no PALplus in the last frame
1
PALplus detected
D2
close caption valid
CCV
0
no closed caption in the last frame
1
closed caption detected
SUBADDRESS
BIT
SYMBOL
DESCRIPTION
61H
D5
F21_N
eld ID as seen by the VBI slicer; for eld 1: D5 = 0
D[4:0]
LN[8:4]
line number
62H
D[7:4]
LN[3:0]
D[3:0]
DT[3:0]
data type; according to Table 14
I-PORT AND SCALER BACK-END CLOCK SELECTION
CONTROL BITS D3 TO D0
ICKS3
ICKS2
ICKS1
ICKS0
ICLK output and back-end clock is line-locked clock LLC from decoder
X
0
ICLK output and back-end clock is XCLK from X-port
X
0
1
ICLK output is LLC and back-end clock is LLC2 clock
X
X(1)
10
Back-end clock is the ICLK input
X
1
IDQ pin carries the data qualier
X
0
X
IDQ pin carries a gated back-end clock (IDQ AND CLK)
X
1
X
IDQ generation only for valid data
0
X
IDQ qualies valid data inside the scaling region and all data outside the scaling
region
1X
X