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參數資料
| 型號： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁數： | 56/144頁 |
| 文件大小： | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
19
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
8.1.3.1
Chrominance path
The 9-bit CVBS or chrominance input signal is fed to the
input of a quadrature demodulator, where it is multiplied by
two time-multiplexed subcarrier signals from the subcarrier
generation block 1 (0
° and 90° phase relationship to the
demodulator axis). The frequency is dependent on the
chosen colour standard.
The time-multiplexed output signals of the multipliers are
low-pass filtered (low-pass 1). Eight characteristics are
programmable via LCWB3 to LCWB0 to achieve the
desired bandwidth for the colour difference signals (PAL,
NTSC) or the 0
° and 90° FM signals (SECAM).
The chrominance low-pass 1 characteristic also influences
the grade of cross-luminance reduction during horizontal
colour transients (large chrominance bandwidth means
strong suppression of cross-luminance). If the Y-comb
filter is disabled by YCOMB = 0 the filter influences directly
the width of the chrominance notch within the luminance
path (large chrominance bandwidth means wide
chrominance notch resulting to lower luminance
bandwidth).
The low-pass filtered signals are fed to the adaptive comb
filter block. The chrominance components are separated
from the luminance via a two line vertical stage (four lines
for PAL standards) and a decision logic between the
filtered and the non-filtered output signals. This block is
bypassed for SECAM signals. The comb filter logic can be
enabled independently for the succeeding luminance and
chrominance processing by YCOMB (subaddress 09H,
bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always
bypassed during VBI or raw data lines programmable by
the LCRn registers (subaddresses 41H to 57H), see
Section 8.2.
The separated UV-components are further processed by a
second filter stage (low-pass 2) to modify the chrominance
bandwidth without influence to the luminance path. It’s
characteristic is controlled by CHBW (subaddress 10H,
bit 3). For the complete transfer characteristic of
low-passes 1 and 2 see Figs 10 and 11.
The SECAM processing (bypassed for QUAM standards)
contains the following blocks:
Baseband ‘bell’ filters to reconstruct the amplitude and
phase equalized 0
° and 90° FM signals
Phase demodulator and differentiator
(FM-demodulation)
De-emphasis filter to compensate the pre-emphasized
input signal, including frequency offset compensation
(DB or DR white carrier values are subtracted from the
signal, controlled by the SECAM switch signal).
The succeeding chrominance gain control block amplifies
or attenuates the UV-signal according to the required
ITU 601/656 levels. It is controlled by the output signal
from the amplitude detection circuit within the burst
processing block.
The burst processing block provides the feedback loop of
the chrominance PLL and contains:
Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
(PAL/NTSC standards only)
Loop filter chrominance gain control
(PAL/NTSC standards only)
Loop filter chrominance PLL (only active for
PAL/NTSC standards)
PAL/SECAM sequence detection, H/2-switch
generation.
The increment generation circuit produces the Discrete
Time Oscillator (DTO) increment for both subcarrier
generation blocks. It contains a division by the increment
of the line-locked clock generator to create a stable
phase-locked sine signal under all conditions (e.g. for
non-standard signals).
The PAL delay line block eliminates crosstalk between the
chrominance channels in accordance with the
PAL standard requirements. For NTSC colour standards
the delay line can be used as an additional vertical filter.
If desired, it can be switched off by DCVF = 1. It is always
disabled during VBI or raw data lines programmable by the
LCRn registers (subaddresses 41H to 47H), see
Section 8.2. The embedded line delay is also used for
SECAM recombination (cross-over switches).
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