
Philips Semiconductors
I2C Interface
File: i2c.fm5, modified 7/25/99
PRELIMINARY INFORMATION
15-5
IIC_CR.SW_MODE_EN. At that point, the SCL and SDA
pins can be controlled by the IIC_CR SDA_OUT and
SCL_OUT bits. Writing a ‘1’ to either bit causes the cor-
responding pin to become active, i.e. be pulled low. The
SDA and SCL lines are open-collector outputs, and can
hence also be pulled low by external devices. The actual
pin state can be observed by software by examining
IIC_SR SDA_STAT and SCL_STAT bits. A 1 in these
MMIO bits indicates that the corresponding pin is cur-
rently pulled low.
By appropriate software, possibly using a timer interrupt,
full I2C functionality can be implemented using this
mechanism.
15.6
I2C HARDWARE OPERATION MODE
Hardware operation of I2C is the default mode after boot.
The TM1100 I2C hardware interface operates in one of
two modes:
1. Master-Transmitter (to write data to a slave)
2. Master-Receiver (to read data from a slave)
As a master, the I2C logic will generate all the serial clock
pulses and the START and STOP bus conditions. The
START and STOP bus conditions are shown in
or a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the I2C bus will not be released.
Note:
The I2C interface on TM1100 will operate as a
master ONLY!
The number of bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each data byte of 8 bits is followed by one ac-
knowledge bit. The transmitter releases the SDA line
which will pull-up to a HIGH level during the acknowl-
edge bit time. The receiver acknowledges by pulling the
data line LOW during this acknowledge period. The mas-
ter must always generate the SCL transitions for the ac-
knowledge bit time.
Two types of data transfers are supported by the
TM1100 I2C interface:
SCL
SDA
hardware
DATA
HIWAY
open drain
scl_stat
scl_out
I2C
DQ
sda_stat
sda_out
tribuf
sw_mode_en
buf
open drain
buf
DQ
Figure 15-3. I2C software mode only logic
SDA
SCL
S
P
START
STOP
Figure 15-4. START and STOP Conditions on I2C