
File: endian.fm5, modified 7/23/99
PRELIMINARY INFORMATION
C-1
Endian-ness
Appendix C
by Selliah Rathnam, Luis Lucas
C.1
PURPOSE
TM1100 has been designed in order to support both Lit-
tle and Big Endian systems. The PCI system bus (con-
trolled by the BIU unit) operates in Little Endian mode in
both systems. This document describes how the dual en-
dian-ness feature is handled in TM1100.
C.2
LITTLE AND BIG ENDIAN
ADDRESSING CONVENTIONS
In Big Endian mode, a given word address (32-bit) base
corresponds to the most significant byte (MSB) of the
word. Increasing the byte address generally means de-
creasing the significance of the byte being accessed. In
Little Endian mode, the same word address base refers
to the least significant byte (LSB) of that word. Increasing
the byte address generally means increasing the signifi-
cance of the byte being accessed. This addressing con-
In
Figure C-1, there is a two-line ‘C’ code which defines
a 32-bit constant in hex format assigned to the variable
‘w’ (assumes “int” is 32-bit) and its address is copied into
the byte (character) pointer variable “cp”. The value of
address referenced by the “cp” has a value of “0x04” in
Big Endian machine and a value of “0x07” in Little Endian
machine.
It is possible to transfer from one endian-ness to another
just by swapping the bytes within a word as shown in
Fig-int w = 0x04050607;
char *cp = (char *)&w;
Figure C-1. Big and Little Endian address references
0
31
04
05
06
07
Big Endian Mode
Little Endian Mode
cp+0
04
05
06
07
cp+3
cp+1
cp+2
cp+3
cp+2
cp+1
cp+0
0
31
Figure C-2. Data conversion from Big Endian to Little Endian (BSW)
int w = 0x04050607;
char *cp = (char *)&w;
0
31
07
06
05
04
Big Endian Mode
Little Endian Mode
cp+0
04
05
06
07
cp+3
cp+1
cp+2
cp+3
cp+2
cp+1
cp+0
0
31