
TM1100 Preliminary Data Book
Philips Semiconductors
A-32
PRELIMINARY INFORMATION
File: ops.fm5, modified 7/23/99
Quad clipped add of unsigned/signed bytes
SYNTAX
[ IF r
guard ] dspuquadaddui rsrc1 rsrc2
→ rdest
FUNCTION
if r
guard then {
for (i
← 0, m ← 31, n ← 24; i < 4; i ← i + 1, m ← m – 8, n ← n – 8) {
temp
← zero_ext8to32(rsrc1<m:n>) + sign_ext8to32(rsrc2<m:n>)
if temp < 0 then
r
dest<m:n>
← 0
else if temp > 0xff then
r
dest<m:n>
← 0xff
else r
dest<m:n>
← temp<7:0>
}
ATTRIBUTES
Function unit
dspalu
Operation code
78
Number of operands
2
Modier
No
Modier range
—
Latency
2
Issue slots
1, 3
DESCRIPTION
As shown below, the dspuquadaddui operation computes four separate sums of the four pairs of corresponding
8-bit bytes of r
src1 and rsrc2. The bytes in rsrc1 are considered unsigned values; the bytes in rsrc2 are considered
signed. The four sums are clipped into the unsigned range [255..0] (or [0xff..0]); thus, the nal byte sums are
unsigned. All computations are performed without loss of precision.
The dspuquadaddui operation optionally takes a guard, specied in r
guard. If a guard is present, its LSB
controls the modication of the destination register. If the LSB of r
guard is 1, rdest is written; otherwise, rdest is not
changed.
EXAMPLES
Initial Values
Operation
Result
r30 = 0x02010001, r40 = 0xffffff01
dspuquadaddui r30 r40
→ r50
r50
← 0x01000002
r10 = 0, r60 = 0x9c9c6464, r70 = 0x649c649c
IF r10 dspuquadaddui r60 r70
→ r80 no change, since guard is
false
r20 = 1, r60 = 0x9c9c6464, r70 = 0x649c649c
IF r20 dspuquadaddui r60 r70
→ r90 r90 ← 0xff38c800
0
1
3
r
src1
0
1
3
r
src2
0
3
r
dest
+
27
7
1
2
0
9
0
9
0
9
0
9
Four full-precision
10-bit signed sums
Clip to [255..0]
unsigned
signed
unsigned
Clip to [255..0]
SEE ALSO
dspuquadaddui