
Philips Semiconductors
Overview
File: intro.fm5, modified 7/23/99
PRELIMINARY INFORMATION
2-5
ICP in memory-to-PCI mode to perform horizontal resiz-
ing and optional colorspace conversion from YUV to
RGB.
While sending the final, resampled and converted pixels
over the PCI bus to the video frame buffer, the ICP uses
a full, per-pixel occlusion bit mask—accessed in destina-
tion coordinates—to determine which pixels are actually
written to the graphics card frame buffer for display. Con-
ditioning the transfer with the bit mask allows TM1100 to
accommodate an arbitrary arrangement of overlapping
windows on the PC video screen.
Figure 2-3 illustrates a possible display situation and the
data structures in SDRAM that support the ICP’s opera-
tion. On the left in
Figure 2-3, the PC’s video screen has
four overlapping windows. Two, Image 1 and Image 2,
are being used to display video generated by TM1100.
The right side of
Figure 2-3 shows a conceptual view of
SDRAM contents. Two data structures are present, one
for Image 1 and the other for Image 2.
Figure 2-3 repre-
sents a point in time during which the ICP is displaying
Image 2.
When the ICP is displaying an image (i.e., copying it from
SDRAM to a frame buffer), it maintains four pointers to
the data structures in SDRAM. Three pointers locate the
Y, U, and V data arrays, and the fourth locates the per-
pixel occlusion bit map. The Y, U, and V arrays are in-
dexed by source coordinates while the occlusion bit map
is accessed with screen coordinates.
As the ICP generates pixels for display, it performs hori-
zontal scaling and colorspace conversion. The final RGB
pixel value is then copied to the destination address in
the screen’s frame buffer only if the corresponding bit in
the occlusion bit map is a one.
As shown in the conceptual diagram, the occlusion bit
map has a pattern of 1s and 0s that corresponds to the
shape of the visible area of the destination window in the
frame buffer. When the arrangement of windows on the
PC screen is changed, modifications to the occlusion bit
maps are performed by TM1100 or host resident soft-
ware.
It is important to note that there is no preset limit on the
number and sizes of windows that can be handled by the
ICP. The only limit is the available bandwidth. Thus, the
ICP can handle a few large windows or many small win-
dows. The ICP can sustain a transfer rate of 50 megapix-
els per second, which is more than enough to saturate
PCI when transferring images to video frame buffers.
2.5.6
Variable-Length Decoder (VLD)
The variable-length decoder (VLD) is included to relieve
the DSPCPU of the task of decoding Huffman-encoded
video data streams. It can be used to help decode high
bitrate MPEG-1 and MPEG-2 video streams. The lower
bitrate of video-conferencing can be adequately handled
by DSPCPU software without co-processor.
The VLD is a memory-to-memory coprocessor. The
DSPCPU hands the VLD a pointer to a Huffman-encod-
ed bit stream, and the VLD produces a tokenized bit
stream that is very convenient for the TM1100 image de-
compression software to use. The format of the output
token stream is optimized for the MPEG-2 decompres-
sion software so that communication between the
DSPCPU and VLD is minimized.
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PC Screen
Image 1
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Format View
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FrameMaker 5
IMAGE 1
Calendar
In SDRAM
Image 2
Y
U
V
Y
U
V
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Image 1
Image 2
ICP
Figure 2-3. ICP - Windows on the PC screen and data structures in SDRAM for two live video windows.