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參數(shù)資料
| 型號(hào)： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數(shù)： | 10/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–10–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Function
16
P2/SW2
Dual-Purpose Pin. It can act as a general purpose output (P2) bit referenced between AV
DD
and
AGND or as a low-side power switch (SW2) to PWRGND.
Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND.
Dual-Purpose Pin. It can act as a general-purpose output (P1) bit referenced between AV
DD
and
AGND or as a low-side power switch (SW1) to PWRGND.
Digital Input Used to Reset the ADC to Its Power-On-Reset Status. This pin has a weak pull-up
internally to DV
DD
.
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt triggered
input making the interface suitable for opto-isolated applications. The serial clock can be continuous
with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous
clock with the information being transmitted to or from the AD7719 in smaller batches of data. A
weak pull-up to DV
DD
is provided on the SCLK input.
Chip Select Input. This is an active low logic input used to select the AD7719. CS can be used to
select the AD7719 in systems with more than one device on the serial bus or as a frame synchroniza-
tion signal in communicating with the device. CS can be hardwired low allowing the AD7719 to be
operated in 3-wire mode with SCLK, DIN and DOUT used to interface with the device. A weak
pull-up to DV
DD
is provided on the CS input.
RDY is a Logic Low Status Output from the AD7719. RDY is low if either the Main ADC or auxil-
iary ADC channel has valid data in their data register. This output returns high on completion of a
read operation from the data register. If data is not read, RDY will return high prior to the next up-
date indicating to the user that a read operation should not be initiated. The RDY pin also returns
low following the completion of a calibration cycle. The RDY pin is effectively the digital NOR func-
tion of the RDY0 and RDY1 bits in the Status register. If one of the ADCs is disabled the RDY pin
reflects the active ADC. RDY does not return high after a calibration until the mode bits are written
to enabling a new conversion or calibration. Since the RDY pin provides information on both the
main and aux ADCs, therefore, when either the main or aux ADC is disabled it is recommended to
immediately read its data register to ensure that its RDY bit goes inactive and releases the RDY pin
to indicate output data updates on the remaining active ADC.
Serial Data Output Accessing the Output Shift Register of the AD7719. The output shift register can
contain data from any of the on-chip data, calibration or control registers.
Serial Data Input Accessing the Input Shift Register on the AD7719. Data in this shift register is
transferred to the calibration or control registers within the ADC depending on the selection bits of
the Communications register. A weak pull-up to DV
DD
is provided on the DIN input.
Ground Reference Point for the Digital Circuitry.
Digital Supply Voltage, 3 V or 5 V Nominal.
Output from the 32 kHz Crystal Oscillator Inverter.
Input to the 32 kHz Crystal Oscillator Inverter.
17
18
PWRGND
P1/SW1
19
RESET
20
SCLK
21
CS
22
RDY
23
DOUT
24
DIN
25
26
27
28
DGND
DV
DD
XTAL2
XTAL1
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