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參數(shù)資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–7–
TIMING CHARACTERISTICS
1, 2
5.25 V; AGND = DGND = 0 V; X
TAL
= 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.)
Limit at T
MIN
, T
MAX
(B Version)
Parameter
Unit
Conditions/Comments
t
1
t
2
Read Operation
t
3
t
4
t
54
32.768
50
kHz typ
ns min
Crystal Oscillator Frequency.
RESET
Pulsewidth
0
0
0
60
80
0
60
80
100
100
0
10
80
100
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
RDY
to
CS
Setup Time
CS
Falling Edge to SCLK Active Edge Setup Time
3
SCLK Active Edge to Data Valid Delay
3
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
CS
Falling Edge to Data Valid Delay
3
DV
DD
= 4.75 V to 5.25 V
DV
DD
= 2.7 V to 3.6 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Inactive Edge Hold Time
3
Bus Relinquish Time after SCLK Inactive Edge
3
t
5A4, 5
t
6
t
7
t
8
t
96
t
10
SCLK Active Edge to
RDY
High
3, 7
Write Operation
t
11
t
12
t
13
t
14
t
15
t
16
0
30
25
100
100
0
ns min
ns min
ns min
ns min
ns min
ns min
CS
Falling Edge to SCLK Active Edge Setup Time
3
Data Valid to SCLK Edge Setup Time
Data Valid to SCLK Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to SCLK Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
2
See Figures 2 and 3.
3
SCLK active edge is falling edge of SCLK.
4
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
or V
OH
limits.
5
This specification only comes into play if
CS
goes low while SCLK is low. It is required primarily for interfacing to DSP machines.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapo-
lated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the
part and as such are independent of external bus loading capacitances.
7
RDY
returns high after a read of both ADCs. The same data can be read again, if required, while
RDY
is high, although care should be taken that subsequent reads do not occur
close to the next output update.
(AV
DD
= 2.7 V to 3.6 V or AV
DD
= 4.75 V to 5.25 V; DV
DD
= 2.7 V to 3.6 V or DV
DD
= 4.75 V to
I
SINK
(1.6mA WITH DV
DD
= 5V
100 A WITH DV
DD
= 3V)
1.6V
I
SOURCE
(200 A WITH DV
DD
= 5V
100 A WITH DV
DD
= 3V)
TO OUTPUT
PIN
50pF
Figure 1. Load Circuit for Timing Characterization
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7719 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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