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參數資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數： | 12/40頁 |
| 文件大?。?/td> | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–12–
OSCILLATOR
AV
= DV
DD
= 5V
T
A
= 25 C
TIME BASE = 100ms/DIV
TRACE 1 = TRACE 2 = 2V/DIV
V
DD
TPC 7. Typical Oscillator Power-Up
DUAL-CHANNEL ADC CIRCUIT INFORMATION
Overview
The AD7719 incorporates two independent
Σ
-
ADC channels
(main and auxiliary) with on-chip digital filtering intended for
the measurement of wide dynamic range, low frequency signals
such as those in weigh-scale, strain-gauge, pressure transducer,
or temperature measurement applications.
Main Channel
This channel is intended to convert the primary sensor input.
This channel can be operated in buffered or unbuffered mode
and can be programmed to have one of eight input voltage ranges
from
±
20 mV to
±
2.56 V. This channel can be configured as
either two fully differential inputs (AIN1/AIN2 and AIN3/AIN4)
or three pseudo-differential input channels (AIN1/AIN4, AIN2/
AIN4, and AIN3/AIN4). Buffering the input channel means that
the part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required. Oper-
ating in unbuffered mode leads to lower power consumption in
low power applications, but care must be exercised in unbuffered
mode as source impedances can introduce gain errors. The main
ADC also features sensor burnout currents that can be switched
on and off. These currents can be used to check that a transducer
is still operational before attempting to take measurements.
The ADC employs a sigma-delta conversion technique to realize
up to 24 bits of no-missing-codes performance. The sigma-delta
modulator converts the sampled input signal into a digital pulse
train whose duty cycle contains the digital information. A Sinc
3
programmable low-pass filter is then employed to decimate the
modulator output data stream to give a valid data conversion
result at programmable output rates from 5.35 Hz (186.77 ms)
to 105.0 3 Hz (9.52 ms). A chopping scheme is also employed
to minimize ADC channel offset errors. A block diagram of the
Main ADC input channel is shown in Figure 4. The sampling
frequency of the modulator loop is many times higher than the
bandwidth of the input signal. The integrator in the modulator
shapes the quantization noise (which results from the analog-to-
digital conversion) so that the noise is pushed toward one-half of
the modulator frequency. The output of the sigma-delta modu-
lator feeds directly into the digital filter. The digital filter then
band-limits the response to a frequency significantly lower than
one-half of the modulator frequency. In this manner, the 1-bit
output of the comparator is translated into a bandlimited, low
noise output from the AD7719 ADC. The AD7719 filter is a
low-pass, Sinc
3
or (SIN(x)/x)
3
filter whose primary function is to
remove the quantization noise introduced at the modulator. The
cutoff frequency and decimated output data rate of the filter are
programmable via the SF word loaded to the filter register.
A chopping scheme is employed where the complete signal chain is
chopped, resulting in excellent dc offset and offset drift specifi-
cations, and is extremely beneficial in applications where drift, noise
rejection, and optimum EMI rejection are important factors.
With chopping the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc
3
filters therefore
have a positive offset and negative offset term included. As a result,
a final summing stage is included so that each output word from
the filter is summed and averaged with the previous filter output
to produce a new valid output result to be written to the ADC
data register.
Auxiliary Channel
The Auxiliary (Aux) channel is intended to convert supplemen-
tary inputs such as from a cold junction diode or thermistor.
This channel is unbuffered and has an input range of
±
REFIN2
or
±
REFIN2/2 determined by the ARN bit in the auxiliary ADC
control register (AD1CON). AIN3 and AIN4 can be multiplexed
into the auxiliary channel as single ended inputs with respect to
AGND while AIN5 and AIN6 can operate as a differential input
pair or with AIN6 tied to AGND, AIN5 can be operated as an
additional single-ended input. A block diagram of the Auxiliary
ADC channel is shown in Figure 5.
SINC
3
FILTER
MUX
BUF
PGA
S-D
MOD0
XOR
ANALOG
INPUT
DIGITAL
OUTPUT
1
8
SF
3
(
)
(8
SF
)
3
1
2
A
IN
+ V
OS
A
IN
–
V
OS
f
CHOP
f
IN
f
MOD
f
CHOP
f
ADC
Figure 4. Main ADC Channel Block Diagram
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| AD7720BRU | CMOS Sigma-Delta Modulator |
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