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參數資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數： | 14/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–14–
FREQUENCY
–
Hz
0
–
80
–
160
0
100
10
A
–
20
30
40
50
60
70
80
90
–
20
–
40
–
120
–
140
–
60
–
100
SF = 69
OUTPUT DATA RATE = 19.8Hz
INPUT BANDWIDTH = 4.74Hz
FIRST NOTCH = 9.9Hz
50Hz REJECTION =
–
66dB, 50Hz 1Hz REJECTION =
–
60dB
60Hz REJECTION =
–
117dB, 60Hz 1Hz REJECTION =
–
94dB
Figure 8. Filter Profile with Default SF = 69 Giving Filter
Notches at Both 50 Hz and 60 Hz
FREQUENCY
–
Hz
0
–
80
–
160
0
100
10
A
–
20
30
40
50
60
70
80
90
–
20
–
40
–
120
–
140
–
60
–
100
SF = 255
OUTPUT DATA RATE = 5.35Hz
INPUT BANDWIDTH = 1.28Hz
50Hz REJECTION =
–
93dB, 50Hz 1Hz REJECTION =
–
93dB
60Hz REJECTION =
–
74dB, 60Hz 1Hz REJECTION =
–
68dB
Figure 9. Filter Profile with SF = 255
FREQUENCY
–
Hz
0
–
140
–
200
0
650
50 100 150 200 250 300 350 400 450 500 550 600
700
A
–
–
20
–
120
–
160
–
180
–
60
–
100
–
40
–
80
SF = 13
OUTPUT DATA RATE = 105Hz
INPUT BANDWIDTH = 25.2Hz
FIRST NOTCH = 52.5Hz
50Hz REJECTION =
–
23.6dB, 50Hz 1Hz REJECTION =
–
20.5dB
60Hz REJECTION =
–
14.6dB, 60Hz 1Hz REJECTION =
–
13.6dB
Figure 6. Filter Profile with SF = 13
FREQUENCY
–
Hz
0
–
80
–
160
0
100
10
A
–
20
30
40
50
60
70
80
90
–
20
–
40
–
120
–
140
–
60
–
100
SF = 82
OUTPUT DATA RATE = 16.65Hz
INPUT BANDWIDTH = 4Hz
50Hz REJECTION =
–
171dB, 50Hz 1Hz REJECTION =
–
100dB
60Hz REJECTION =
–
58dB, 60Hz 1Hz REJECTION =
–
53dB
Figure 7. Filter Profile with SF = 82
MAIN AND AUXILIARY ADC NOISE PERFORMANCE
Tables II to VII show the output rms noise and output peak-to-
peak resolution in bits (rounded to the nearest 0.5 LSB) for a
selection of output update rates on both the main and auxiliary
ADCs. The numbers are typical and generated at a differential
input voltage of 0 V. The output update rate is selected via the
SF7-SF0 bits in the Filter Register. It is important to note that
the peak-to-peak resolution figures represent the resolution for
which there will be no code flicker within a six-sigma limit. The
output noise comes from two sources. The first is the electrical
noise in the semiconductor devices (device noise) used in the
implementation of the modulator. Secondly, when the analog
input is converted into the digital domain, quantization noise is
added. The device noise is at a low level and is independent of
frequency. The quantization noise starts at an even lower level
but rises rapidly with increasing frequency to become the domi-
nant noise source. The numbers in the tables are given for the
bipolar input ranges. For the unipolar ranges the rms noise
numbers will be the same as the bipolar range, but the peak-to-
peak resolution is now based on half the signal range, which
effectively means losing 1 bit of resolution.
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