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參數(shù)資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–20–
Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 00 Hex)
The ADC Status Register is an 8-bit read-only register. To access the ADC Status Register, the user must write to the Communica-
tions Register selecting the next operation to be a read and load bits A3
–
A0 with 0, 0, 0, 0. Table XI outlines the bit designations for
the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 denotes the first
bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.
7
R
S
6
R
S
5
R
S
4
R
S
3
R
S
2
R
S
1
R
S
0
R
S
)
0
(
0
Y
D
R
)
0
(
1
Y
D
R
)
0
(
L
A
C
)
0
(
F
E
R
X
O
N
)
0
(
0
R
R
E
)
0
(
1
R
R
E
)
0
(
)
0
(
K
C
O
L
Table XI. Status Register Bit Designations
Bit
Location
Bit
Name
Description
SR7
RDY0
Ready Bit for Main ADC.
Set
when data is written to Main ADC data registers or on completion of calibration cycle. The RDY0 bit
is
cleared
automatically after the Main ADC data register has been read or a period of time before the data
register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to
indicate a conversion or calibration.
Ready Bit for Aux ADC.
Set
when data is written to Aux ADC data registers or on completion of calibration cycle. The RDY1 bit
is
cleared
automatically after the Aux ADC data register has been read or a period of time before the data
register is updated with a new conversion result. This bit is also cleared by a write to the mode bits to
indicate a conversion or calibration.
Calibration Status Bit.
Set
to indicate completion of calibration. It is set at the same time that the RDY0 and/or RDY1 bits
are set high.
Cleared
by a write to the mode bits to start another ADC conversion or calibration.
No External Reference Bit. (
Only active if Main ADC is active and applies to REFIN1 only.
)
Set
to indicate that one or both of the REFIN1 pins is floating or the applied voltage is below a specified
threshold. When
Set,
conversion results are clamped to all ones.
Cleared
to indicate valid Reference applied between REFIN1(+) and REFIN1(
–
).
Main ADC Error Bit.
Set
to indicate that the result written to the Main ADC data registers has been clamped to all zeros or all
ones. After a calibration this bit also flags error conditions that caused the calibration registers not to be
written. Error sources include Overrange, Underrange and NOXREF.
Cleared
by a write to the mode bits to initiate a conversion or calibration.
Aux ADC Error Bit.
Set
to indicate that the result written to the Aux ADC data registers has been clamped to all zeros or all
ones. After a calibration this bit also flags error conditions that caused the calibration registers not to be
written. Error sources include Overrange, Underrange, and NOXREF.
Cleared
by a write to the mode bits to initiate a conversion or calibration.
Reserved for Future Use.
PLL Lock Status Bit.
Set
if the PLL has locked onto the 32 kHz crystal oscillator clock. If the user is worried about exact sampling
frequencies etc., the LOCK bit should be interrogated and the result discarded if the LOCK bit is zero.
SR6
RDY1
SR5
CAL
SR4
NOXREF
SR3
ERR0
SR2
ERR1
SR1
SR0
0
LOCK
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