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參數資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數： | 32/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–32–
The absolute input voltage range on the auxiliary ADC and the
main ADC in unbuffered mode includes the range between
AGND
–
30 mV to AV
DD
+ 30 mV as a result of being unbuf-
fered. The negative absolute input voltage limit does allow
the possibility of monitoring small true bipolar signals with
respect to AGND.
Programmable Gain Amplifier
The output from the buffer on the main ADC is applied to the
input of the on-chip programmable gain amplifier (PGA). The
PGA can be programmed through eight different unipolar and
bipolar ranges. The PGA gain range is programmed via the
range bits in the ADC0CON register. With an external 2.5 V
reference applied the unipolar ranges are 0 mV to 20 mV, 0 to
40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV,
0 mV to 640 mV, 0 V to 1.28 V and 0 to 2.56 V while bipolar
ranges are
±
20 mV,
±
40 mV,
±
80 mV,
±
160 mV,
±
320 mV,
±
640 mV,
±
1.28 V and
±
2.56 V. These are the ranges that
should appear at the input to the on-chip PGA. The ADC range
matching specification of 2
μ
V (typ) across all ranges means that
calibration need only be carried out on a single range and does
not have to be repeated when the PGA range is changed. This is
a significant advantage when compared with similar ADCs
available on the market.
Typical matching across ranges is shown in Figure 18. Here, the
primary ADC is configured in fully-differential, bipolar mode
with an external 2.5 V reference, while an analog input voltage
of just greater than 19 mV is forced on its analog inputs. The
ADC continuously converts the DC voltage at an update rate of
5.35 Hz, i.e., SF = FF Hex. 800 conversion results in total are
gathered. The first 100 results gathered with the primary ADC
operating in the
±
20 mV. The ADC range is then switched to
±
40 mV and 100 more results are gathered, and so on until the
last 100 samples are gathered with the ADC configured in the
±
2.5 V range. From Figure 18, the variation in the sample mean
through each range, i.e., the range matching, is seen to be on
the order of 2
μ
V.
The auxiliary ADC does not incorporate an eight range PGA.
The aux ADC operates at a gain of 1 or a gain of 2 as deter-
mined by the ARN bit in the AD1CON register.
0
100
200
300
400
500
600
700
800
SAMPLE COUNT
A
–
19.372
19.371
19.370
19.369
19.368
19.367
19.366
19.365
19.364
ADC RANGE
2
4
8
1
3
6
1
2
Figure 18. Main ADC Range Matching
Bipolar/Unipolar Configuration
The analog inputs on the AD7719 can accept either unipolar or
bipolar input voltage ranges. Bipolar input ranges does not imply
that the part can handle negative voltages with respect to system
AGND. Unipolar and bipolar signals on the AIN(+) input on
the main ADC are referenced to the voltage on the respective
AIN(
–
) input. AIN(+) and AIN(
–
) refer to the signals seen by
the modulator that come from the output of the multiplexer as
shown in Figures 16 and 17.
For example, if AIN(
–
) is 2.5 V and the main ADC is config-
ured for an analog input range of 0 mV to 20 mV, the input
voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(
–
)
is 2.5 V and the AD7719 is configured for an analog input range
of
±
1.28 V, the analog input range on the AIN(+) input is 1.22 V
to 3.78 V (i.e., 2.5 V
±
1.28 V). Bipolar or unipolar options are
chosen by programming the main and Auxiliary U/
B
bit in the
ADC0CON and ADC1CON registers respectively. This pro-
grams the relevant ADC for either unipolar or bipolar operation.
Programming for either unipolar or bipolar operation does
not
change any of the input signal conditioning; it simply changes
the
data output coding and the points on the transfer function
where calibrations occur.
Table XVIII. Max Resistance for No 16-Bit Gain Error (Unbuffered Mode)
External Capacitance
100 pF
16.7K
8.1K
3.9K
1.7K
Gain
1
2
4
8
–
128
0 pF
111.3K
53.7K
25.4K
10.7K
50 pF
27.8K
13.5K
6.4K
2.9K
500 pF
4.5K
2.2K
1.0K
480
1000 pF
2.58K
1.26K
600
270
5000 pF
700
360
170
75
Table XIX. Max Resistance for No 20-Bit Gain Error (Unbuffered Mode)
External Capacitance
100 pF
12.5K
6.1K
2.9K
1.3K
Gain
1
2
4
8
–
128
0 pF
84.9K
42.0K
20.5K
8.8K
50 pF
21.1K
10.4K
5.0K
2.3K
500 pF
3.2K
1.6K
790K
370
1000 pF
1.77K
880
430
195
5000 pF
440
220
110
50
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