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參數資料
| 型號： | AD7719BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Low Voltage, Low Power, Factory-Calibrated 16-/24-Bit Dual ADC |
| 中文描述： | 6-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MS-153AE, TSSOP-28 |
| 文件頁數： | 24/40頁 |
| 文件大小： | 367K |
| 代理商： | AD7719BRU |
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REV. 0
AD7719
–24–
Table XIV (continued)
AD1CON3
U/
B
Aux ADC Unipolar/Bipolar Selection Bit.
Set
by user to enable unipolar coding i.e., Zero differential input will result in 0000 Hex output.
Cleared
by user to enable bipolar coding, Zero differential input will result in 8000 Hex output.
AD1CON2
AD1CON1
AD1CON0
0
0
ARN
Must be zero for specified operation.
Must be zero for specified operation.
Auxiliary Channel Input Range Bit.
When
set
by the user the input range is
±
REFIN2.
When
cleared
by the user the input range is
±
REFIN2/2.
NOTES
1. When the temperature sensor is selected, the AD7719 automatically selects its internal reference. The temperature sensor is not factory calibrated. Temp sensor
is suitable for relative temperature measurements. The temperature sensor yields conversion results where a conversion result of 8000H equates to typically 0
°
C.
2. A 1
°
C change in temperature will normally result in a 256 LSB change in the AD1 data register (ADC conversion result).
Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 45 Hex)
The Filter Register is an 8-bit register from which data can be read or to which data can be written. This register determines the
amount of averaging performed by the sinc filter. Table XV outlines the bit designations for the Filter Register. FR7 through FR0
indicate the bit location, FR denoting the bits are in the Filter Register. FR7 denotes the first bit of the data stream. The number in
brackets indicates the power-on/reset default status of that bit. The number in this register is used to set the decimation factor and
thus the output update rate for the Main and Aux ADCs. The filter register cannot be written to by the user while either ADC is
active. The update rate is used for both Main and Aux ADCs and is calculated as follows:
f
SF
f
ADC
MOD
=
×
×
×
1
3
1
8
where
f
ADC
= ADC Output Update Rate.
f
MOD
= Modulator Clock Frequency = 32.768 kHz (Main and Aux ADC)
SF
= Decimal Value Written to SF Register.
The allowable range for SF is 13dec to 255dec. Examples of SF values and corresponding conversion rate (f
ADC
) and time (t
ADC
) are
shown in Table XV. It should also be noted that both ADC input channels are chopped to minimize offset errors. This means that
the time for a single conversion or the time to the first conversion result is 2
×
t
ADC
.
Table XV. Update Rate vs. SF WORD
SF (dec)
SF (Hex)
f
ADC
(Hz)
t
ADC
(ms)
13
69
255
0D
45
FF
105.3
19.79
5.35
9.52
50.34
186.77
I/O and Current Source Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On Reset = 0000 Hex)
The IOCON Register is a 16-bit register from which data can be read or to which data can be written. This register is used to control
and configure the various excitation and burnout current source options available on-chip along with controlling the I/O port. Table
XVI outlines the bit designations for this register. IOCON15 through IOCON0 indicate the bit location, IOCON denoting the bits
are in the I/O and Current Source Control Register. IOCON15 denotes the first bit of the data stream. The number in brackets
indicates the power-on/reset default status of that bit. A write to the IOCON register has immediate effect and does not reset the
ADCs. Thus, if a current source is switched while the ADC is converting the user will have to wait for the full settling time of the
filter before getting a fully-settled output. Since the ADC is chopped this equates to three outputs.
5
)
1
0
N
(
O
2
C
W
S
O
P
I
4
)
1
0
N
(
O
1
C
W
S
O
P
I
3
1
N
)
O
(
C
0
O
I
2
1
)
N
0
(
O
C
O
B
O
I
1
)
1
0
N
(
O
N
I
C
P
O
2
I
I
0
)
1
1
N
(
O
N
I
C
P
O
1
I
I
9
)
N
0
(
O
N
C
E
O
2
I
I
8
)
N
0
(
O
N
C
E
O
1
I
I
0
7
0
N
(
O
R
I
C
D
O
4
I
6
0
N
(
O
R
I
C
D
O
3
I
5
)
N
(
O
N
C
E
O
2
I
P
4
)
N
(
O
N
C
E
O
1
I
P
3
0
N
O
T
A
C
O
D
4
I
2
0
N
O
T
A
C
O
D
3
I
1
0
N
O
T
A
C
O
D
2
I
0
0
N
O
T
A
C
O
D
1
I
)
P
)
P
0
0
)
(
P
)
(
P
)
(
P
)
(
P
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
SF7 (0)
SF6 (1)
SF5 (0)
SF4 (0)
SF3 (0)
SF2 (1)
SF1 (0)
SF0 (1)
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