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參數資料
| 型號： | AD7725 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| 中文描述： | 16位900 ksps模數轉換器的可編程后處理器 |
| 文件頁數： | 26/28頁 |
| 文件大小： | 442K |
| 代理商： | AD7725 |
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REV. A
–26–
AD7725
Converting
When the ADCs are converting, the conversion result of the
first device in the chain is sent to the second device and is com-
bined with the conversion data of the second device by the
interlacer. This data is then combined with the data from the
next device in the chain, and so on. The output from the last
device will be a continuous serial data stream consisting of the
conversion results of all the devices in the chain. A single DSP
can read back all the conversion data in the sequence:
Device N; ... Device 2; Device 1; Device N; ... Device 2;
Device 1; and so on.
Figure 33 shows a connection diagram for daisy-chaining multiple
devices with a common DSP, and Figure 34 shows a connection
diagram for daisy-chaining multiple devices with a common DSP
and a shared EPROM.
AD7725
SDI
FSI
FSO
SDO
CFGEND
INIT
DSP MODE
SOE
SCO
AD7725
ADSP-21xx
SCLK0
RFS0
DR0
DT0
TFS0
IRQ1
FSO
SDO
SDI
FSI
CFGEND
INIT
S
DSP MODE
SOE
SCO
Figure 33. Daisy-Chaining Devices with a Common DSP
XC1700D
CLK
DAT
CEO
OE
CE
AD7725
AD7725
FSO
SDO
SDI
FSI
SDI
FSI
FSO
SDO
CFGEND
INIT
CFGEND
INIT
EPROM
MODE
DSP MODE
SOE
SCO
SCO
ADSP-21xx
SCLK0
RFS0
DR0
SPORT0
SOE
Figure 34. Daisy-Chaining Devices with a Common DSP
and a Shared EPROM
Cascading Filters across Multiple Devices
If the design of a filter is too large for one AD7725 device to
handle, the filter can be cascaded across multiple devices.
For example, if you have a 3-stage filter in your design that
requires over 108 taps to be implemented, this filter can be
shared between two or three devices. To do this, a configura-
tion file needs to be developed in Filter Wizard. Filter Wizard
allows the user to split the filter stages up and implement
them on different devices with the output of the final device
being the filtered input of the first device.
SERIAL INTERFACE TO A DSP
In serial mode, the AD7725 can be directly interfaced to several
industry-standard digital signal processors. In all cases, the
AD7725 operates as the master with the DSP operating as a slave.
The AD7725 provides its own serial clock (SCO) to transmit the
digital words on the SDO pin to the DSP. The AD7725 also gen-
erates the frame synchronization signal that synchronizes the
transfer of the 16-bit word from the AD7725 to a DSP. SCO will
have a frequency equal to CLKIN or CLKIN/2 depending on the
state of the SCR pin.
AD7725 to ADSP-21xx Interface
Figure 35 shows the interface between the ADSP-21xx and the
AD7725. For the ADSP-21xx, the bits in the serial port control
register should be set up as RFSR and TFSR = 1 (a frame sync
is required for each data transfer), SLEN = 15 (16-bit word
lengths), RFSW and TFSW = 0 (normal framing mode for
receive and transmit operations), INVRFS and INVTFS = 0
(active high RFS and TFS), IRFS = 0 (external RFS), ITFS = 1
(internal TFS), and ISCLK = 0 (external serial clock).
AD7725
*
SCO
FSO
SCLK
DR
RFS
TFS
ADSP-21xx
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
SDO
SDI
FSI
DT
Figure 35. AD7725 to ADSP-21xx Interface
GROUNDING AND LAYOUT
The analog and digital power supplies to the AD7725 are inde-
pendent and separately pinned out to minimize coupling between
analog and digital sections within the device. All the AD7725
AGND and DGND pins should be soldered directly to a ground
plane to minimize series inductance. In addition, the ac path
from any supply pin or reference pin (REF1 and REF2) through
its decoupling capacitors to its associated ground must be made
as short as possible (Figure 36). To achieve the best decoupling,
place surface-mount capacitors as close as possible to the device,
ideally right up against the device pins.
To avoid capacitive coupling, ground planes must not over-
lap. The AD7725’s digital and analog ground planes must be
connected at one place by a low inductance path, preferably
right under the device. Typically, this connection will either
be a trace on the printed circuit board of 0.5 cm wide when
the ground planes are on the same layer, or plated through
holes with an equivalent resistance of a 0.5 cm track when
the ground planes are on different layers. Any external logic
connected to the AD7725 should use a ground plane separate
from the AD7725’s digital ground plane. These two digital
ground planes should also be connected at just one place.
Separate power supplies for AV
DD
and DV
DD
are also highly
desirable. The digital supply pin DV
DD
should be powered from
a separate analog supply, but, if necessary, DV
DD
may share its
power connection to AV
DD
.
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