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參數資料
| 型號： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 13/32頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–13–
Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Rate
Horizontal
Frequency
Standard
Resolution
640
×
480
Pixel Rate
VCORNGE
CURRENT
VGA
60 Hz
72 Hz
75 Hz
85 Hz
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
00
00
00
00
101
101
110
110
SVGA
800
×
600
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
00
01
01
01
01
101
101
101
101
110
XGA
1024
×
768
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
01
10
10
10
10
110
101
101
101
101
SXGA
1280
×
1024
60 Hz
75 Hz
85 Hz
64.0 kHz
80.0 kHz
91.1 kHz
108.000 MHz
135.000 MHz
157.500 MHz
*
10
11
10
110
110
110
UXGA
1600
×
1200
60 Hz
65 Hz
70 Hz
75 Hz
85 Hz
75.0 kHz
81.3 kHz
87.5 kHz
93.8 kHz
106.3 kHz
162.000 MHz
*
175.500 MHz
*
189.000 MHz
*
202.500 MHz
*
229.500 MHz
*
10
10
10
10
11
110
110
110
110
110
*
Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
Table II. VCO Frequency Ranges
Pixel Clock
Range (MHz)
K
VCO
Gain
(MHz/V)
PV1
PV0
0
0
1
1
0
1
0
1
12–35
35–70
70–110
110–140
150
150
150
180
3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table III.
Table III. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current ( A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
provides 32 phase-shift steps of 11.25
°
each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal. This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The
polarity of the COAST signal may be set through the Coast
Polarity Register. Also, the polarity of the Hsync signal may
be set through the HSYNC Polarity Register. For both
HSYNC and COAST, a value of “1” inverts the signal.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
| AD9887AKS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
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