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參數資料
| 型號： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 20/32頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–20–
Table V. Control Register Map (Continued)
Write and
Read or
Read Only
Hex
Address
Default
Value
Register
Name
Bits
Function
0FH
W
/R
7:0
1
*******
PLL and
Clamp Control
Bit 7—HSYNC Polarity. Changes polarity of incoming Hsync
signal. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 6—Coast Polarity. Changes polarity of external COAST signal.
(Logic = 0 = Active Low, Logic 1 = Active High.)
Bit 5—Clamp Function. Chooses between HSYNC for Clamp signal
or another external signal to be used for clamping. (Logic 0 = HSYNC,
Logic 1 = Clamp.)
Bit 4—Clamp Polarity. Valid only with external CLAMP signal.
(Logic 0 = Active Low, Logic 1 selects Active High.)
Bit 3—EXTCLK. Shuts down PLL and allows external clock to drive
the part. (Logic 0 = use internal PLL, Logic 1 = bypassing of the
internal PLL.)
Bit 2—Red Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 120).
Bit 1—Green Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 111).
Bit 0—Blue Clamp Select—Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 101).
*
1
******
**
0
*****
***
1
****
****
0
***
*****
0
**
******
0
*
*******
0
10H
W
/R
5:2
**
11
****
Bit 5, 4—Output Drive: Selects between high, medium, and low
output drive strength. (Logic 11 or 10 = High, 01 = Medium, and
00 = Low.)
Bit 3—P
DO
: High Impedance Outputs. (Logic 0 = Normal, Logic
1 = High Impedance.)
Bit 2—Sync Detect (SyncDT) Polarity. This bit sets the polarity
for the SyncDT output pin. (Logic 1 = Active High, Logic 0 =
Active Low.)
****
0
***
*****
1
**
11H
RO
7:1
Sync Detect/
Active
Interface
Bit 7—Analog Interface Hsync Detect. It is set to Logic 1 if Hsync
is present on the analog interface, else it is set to Logic 0.
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1
if sync is present on the green video input, else it is set to 0.
Bit 5—Analog Interface Vsync Detect. It is set to Logic 1 if Vsync
is present on the analog interface, else it is set to Logic 0.
Bit 4—Digital Interface clock Detect. It is set to Logic 1 if the
clock is present on the digital interface, else it is set to Logic 0.
Bit 3—AI: Active Interface. This bit indicates which interface is
active. (Logic 0 = Digital Interface, Logic 1 = Analog Interface.)
Bit 2—AHS: Active Hsync. This bit indicates which analog HSYNC
is being used. (Logic 0 = HSYNC Input Pin, Logic 1 = HSYNC
from Sync-on-Green.)
Bit 1—AVS: Active Vsync. This bit indicates which analog VSYNC
is being used. (Logic 0 = VSYNC input pin, Logic 1 = VSYNC from
sync separator.)
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相關代理商/技術參數 |
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|---|---|
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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| AD9887AKS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
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