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參數資料
| 型號： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 28/32頁 |
| 文件大?。?/td> | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–28–
DIGITAL CONTROL
13
7:0
Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many pixel clock pulses the sync
separator must count to before toggling high or low. It
works like a low-pass filter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
The default for this register is 32.
CONTROL BITS
14
2
This register is used to enable the scan function. When
enabled, data can be loaded into the AD9886 outputs
serially with the scan function. The scan function utilizes
three pins (SCAN
IN
, SCAN
OUT
, and SCAN
CLK
). These
pins are described in Table I.
Scan Enable
Table XLI. Scan Enable Settings
Scan Enable
Result
0
1
Scan Function Disabled
Scan Function Enabled
The default for scan enable is 0 (disabled).
1
Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into
the PLL.
14
Table XLII. Coast Input Polarity Override Settings
Override Bit
Result
0
1
Coast Polarity Determined by Chip
Coast Polarity Determined by User
The default for coast polarity override is 0 (polarity
determined by chip).
0
HSYNC Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into
the PLL.
14
Table XLIII. HSYNC Input Polarity Override Settings
Override Bit
Result
0
1
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
The default for Hsync polarity override is 0 (polarity
determined by chip).
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided. Up to four
AD9886 devices may be connected to the 2-wire serial interface,
with each device having a unique address.
The 2-wire serial interface comprises a clock (SCL) and a bidi-
rectional data (SDA) pin. The Analog Flat Panel Interface acts
as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled HIGH by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is LOW. If SDA changes state while SCL
is HIGH, the serial interface interprets that action as a start or
stop sequence.
There are six components to serial bus operation:
Start Signal
Slave Address Byte
Base Register Address Byte
Data Byte to Read or Write
Stop Signal
When the serial interface is inactive (SCL and SDA are HIGH)
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is
HIGH. This signal alerts all slaved devices that a data transfer
sequence is coming.
The first eight bits of data transferred after a start signal com-
prising a 7-bit slave address (the first seven bits) and a single R/
W
bit (the eighth bit). The R/
W
bit indicates the direction of data
transfer, read from (1) or write to (0) the slave device. If the
transmitted slave address matches the address of the device (set
by the state of the SA
1-0
input pins in Table XLIV, the AD9886
acknowledges by bringing SDA LOW on the 9th SCL pulse. If
the addresses do not match, the AD9886 does not acknowledge.
Table XLIV. Serial Port Addresses
Bit 7
A
6
(MSB)
Bit 6
A
5
Bit 5
A
4
Bit 4
A
3
Bit 3
A
2
Bit 2
A
1
Bit 1
A
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9886 does not acknowledge the master device during a
write sequence, the SDA remains HIGH so the master can
generate a stop signal. If the master device does not acknowledge
the AD9886 during a read sequence, the AD9886 interprets this
as “end of data.” The SDA remains HIGH so the master can
generate a stop signal.
Writing data to specific control registers of the AD9886 requires
that the 8-bit address of the control register of interest be written
after the slave address has been established. This control register
address is the base address for subsequent write operations. The
base address autoincrements by one for each byte of data written
after the data byte intended for the base address. If more bytes
are transferred than there are available addresses, the address will
not increment and remain at its maximum value of 1Dh. Any base
address higher than 1Dh will not produce an acknowledge signal.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
| AD9887AKS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
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