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參數(shù)資料
| 型號(hào)： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁(yè)數(shù)： | 14/32頁(yè) |
| 文件大小： | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–14–
ADC
DAC
DAC
7
8
OFFSET
GAIN
REF
x1.2
IN
CLAMP
V
OFF
8
Figure 8. ADC Block Diagram (Single Channel Output)
1V
I
V
(128 CODES)
I
0.5V
V
OFF
(128 CODES)
O
R
0V
0V
O
Figure 9. Relationship of Offset Range to Input Range
SCAN Function
The SCAN function is intended as a pseudo JTAG function for
manufacturing test for the board. The ordinary operation of the
AD9886 is disabled during SCAN.
To enable the SCAN function, set register 14h, bit 2 to 1. To
SCAN in data to all 48 digital outputs, apply 48 serial bits of
data and 48 clocks (typically 5 MHz, max of 20 MHz) to the
SCAN
IN
and SCAN
CLK
pins respectively. The data is shifted
in on the rising edge of SCAN
CLK
. The first serial bit shifted
in will appear at the RED A<7> output after one clock cycle.
After 48 clocks, the first bit is shifted all the way to the BLU
B<0>. The 48th bit will now be at the RED A<7> output. If
SCAN
CLK
continues after 48 cycles, the data will continue to be
shifted from RED A<7> to BLU B<0> and will come out of the
SCAN
OUT
pin as serial data on the falling edge of SCAN
CLK
.
This is illustrated in Figure 10. A setup time (Tsu) of 3 ns
should be plenty and no hold time (Thold) is required (
≥
0 ns).
This is illustrated in Figure 11.
SCANCLK
RED A<7>
BLUE B<0>
SCANOUT
SCANIN
BIT 1
BIT 2
BIT 3
BIT 47
BIT 48
X
BIT 1
BIT 1
BIT 1
BIT 46
BIT 47
BIT 48
X
X
X
X
X
X
BIT 1
BIT 2
X
BIT 1
BIT 2
X
X
X
X
Figure 10. SCAN Timing
T
SU
= 3ns
T
HOLD
= 0ns
SCANCLK
SCANIN
Figure 11. SCAN Setup and Hold
Alternate Pixel Sampling Mode
A Logic 1 input on Clock Invert (CKINV, Pin 94) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
O
O
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O
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O
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E
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Figure 12. Odd and Even Pixels in a Frame
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire
frame in the graphics controller, a complete image can be recon-
structed. This is very similar to the interlacing process that is
employed in broadcast television systems, but the interlacing is
vertical instead of horizontal. The frame data is still presented to
the display at the full desired refresh rate (usually 60 Hz) so no
flicker artifacts added.
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
Figure 13. Odd Pixels from Frame 1
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