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參數資料
| 型號： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁數： | 7/32頁 |
| 文件大小： | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–7–
PIN FUNCTION DETAIL
Inputs
R
AIN
G
AIN
B
AIN
Analog Input for RED Channel
Analog Input for GREEN Channel
Analog Input for BLUE Channel
High-impedance inputs that accept the RED,
GREEN, and BLUE channel graphics signals,
respectively. (The three channels are identi-
cal and can be used for any colors, but colors
are assigned for convenient reference.)
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
Horizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler-
ance voltage (3.3 V), or more than 0.5 V
below ground.
Vertical Sync Input
This is the input for vertical sync.
Sync-on-Green Input
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally gen-
erated threshold, which is set to 0.15 V above
the negative peak of the input signal.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
(This is usually a composite sync signal,
containing both vertical and horizontal sync
information that must be separated before
passing the horizontal sync signal to HSYNC).
When not used, this input should be left
unconnected. For more details on this func-
tion and how it should be configured, refer to
the Sync on Green section.
External Clamp Input
HSYNC
VSYNC
SOGIN
CLAMP
This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typi-
cally during the back porch of the graphics
signal. The CLAMP pin is enabled by setting
control bit EXTCLMP to 1 (the default
power-up is 0). When disabled, this pin is
ignored and the clamp timing is determined
internally by counting a delay and duration
from the trailing edge of the HSYNC input.
The logic sense of this pin is controlled by
CLAMPOL. When not used, this pin must be
grounded and EXTCLMP programmed to 0.
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel
clock generator to stop synchronizing with
HSYNC and continue producing a clock at
its current frequency and phase. This is useful
when processing signals from sources that fail
to produce horizontal sync pulses when in the
vertical interval. The COAST signal is gener-
ally
not
required for PC-generated signals.
The logic sense of this pin is controlled by
COAST Polarity.
When not used, this pin may be grounded
and COAST Polarity programmed to 1, or tied
HIGH (to V
D
through a 10 k
resistor) and
COAST Polarity programmed to 0. COAST
Polarity defaults to 1 at power-up.
External Clock Input (Optional)
This pin may be used to provide an external
clock to the AD9886, in place of the clock
internally generated from HSYNC.
It is enabled by programming EXTCLK to 1.
When an external clock is used, all other inter-
nal functions operate normally. When unused,
this pin should be tied through a 10 k
resistor
to GROUND, and EXTCLK programmed to
0. The clock phase adjustment still operates
when an external clock source is used.
Sampling Clock Inversion (Optional)
This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180
°
. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sam-
pling the odd pixels, then capturing the even
pixels on the subsequent frame.
This pin should be exercised only during
blanking intervals (typically vertical blanking)
as it may produce several samples of corrupted
data during the phase shift.
CKINV should be grounded when not used.
COAST
CKEXT
CKINV
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相關代理商/技術參數 |
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|---|---|
| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
| AD9887AKS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
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