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參數(shù)資料
| 型號(hào)： | AD9886KS-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Analog Interface for Flat Panel Displays |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, MQFP-160 |
| 文件頁(yè)數(shù)： | 27/32頁(yè) |
| 文件大小： | 248K |
| 代理商： | AD9886KS-140 |
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REV. 0
AD9886
–27–
Table XXXII. Active VSYNC Results
Bit 5
(VSYNC
Detect)
Override
AVS
0
1
X
0
0
1
0
1
Bit 2 in 12H
AVS = 0 means Sync separator.
AVS = 1 means VSYNC input.
The override bit is in Register 12H, Bit 3.
7
AIO—Active Interface Override
This bit is used to override the automatic interface selec-
tion (Bit 3 in Register 11H). To override, set this bit to
Logic 1. When overriding, the active interface is set via
Bit 6 in this register.
12
Table XXXIII. Active Interface Override Settings
AIO
Result
0
1
Autodetermines the Active Interface
Override, Bit 6 Determines the Active Interface
The default for this register is 0.
6
AIS—Active Interface Select
This bit is used under two conditions. It is used to select
the active interface when the override bit is set (Bit 7).
Alternately, it is used to determine the active interface
when not overriding but both interfaces are detected.
12
Table XXXIV. Active Interface Select Settings
AIS
Result
0
1
Analog Interface
Digital Interface
The default for this register is 0.
5
Active Hsync Override
This bit is used to override the automatic Hsync selection
(Bit 2 in Register 11H). To override, set this bit to Logic
1. When overriding, the active Hsync is set via Bit 4 in
this register.
12
Table XXXV. Active Hsync Override Settings
Override
Result
0
1
Autodetermines the Active Interface
Override, Bit 4 Determines the Active Interface
The default for this register is 0.
4
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 5). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
12
Table XXXVI. Active HSYNC Select Settings
Select
Result
0
1
HSYNC Input
Sync-on-Green Input
The default for this register is 0.
3
Active VSYNC Override
This bit is used to override the automatic VSYNC selection
(Bit 1 in register 11H). To override, set this bit to Logic 1.
When overriding, the active interface is set via Bit 2 in
this register.
12
Table XXXVII. Active VSYNC Override Settings
Override
Result
0
1
Autodetermines the Active VSYNC
Override, Bit 2 Determines the Active VSYNC
The default for this register is 0.
2
Active VSYNC Select
This bit is used to select the active VSYNC when the
override bit is set (Bit 3).
12
Table XXXVIII. Active VSYNC Select Settings
Select
Result
0
1
VSYNC Input
Sync Separator Output
The default for this register is 0.
1
COAST Select
This bit is used to select the active COAST source. The
choices are the COAST input pin or VSYNC. If VSYNC
is selected the additional decision of using the VSYNC
input pin or the output from the sync separator needs to
be made (Bits 3, 2).
12
Table XXXIX. COAST Select Settings
Select
Result
0
1
COAST Input Pin
VSYNC (See Above Text)
The default for this register is 0.
0
PWRDN
This bit is used to put the chip in full power-down. This
powers down both interfaces. See the section on Power
Management for details of which blocks are actually
powered down. Note, the chip will be unable to detect
incoming activity while fully powered-down.
12
Table XL. Power-Down Settings
Select
Result
0
1
Power-Down
Normal Operation
The default for this register is 1.
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| AD9887 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
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