- 您現在的位置：買賣IC網 > PDF目錄373970 > AD9910_07 (Analog Devices, Inc.) 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer PDF資料下載
參數資料
| 型號： | AD9910_07 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | 1 GSPS的，14位，3.3伏的CMOS直接數字頻率合成 |
| 文件頁數： | 20/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910_07 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
AD9910
Rev. 0 | Page 20 of 60
Table 4. Parallel Port Destination Bits
F<1:0>
D<15:0>
00
D<15:2>
Parameter(s)
14-bit amplitude
parameter (unsigned
integer)
16-bit phase parameter
(unsigned integer)
32-bit frequency
parameter (unsigned
integer)
8-bit amplitude
(unsigned integer)
Comments
Amplitude scales from 0 to 1 2
14
. D<1:0> are not used.
01
D<15:0>
Phase offset ranges from 0 to 2
π
(1 2
16
) radians.
10
D<15:0>
The alignment of the 16-bit data-word with the 32-bit frequency parameter is controlled
by a 4-bit FM gain word in the programming registers.
11
D<15:8>
The MSB of the data-word amplitude aligns with the MSB of the DDS 14-bit amplitude
parameter. The 6 LSBs of the DDS amplitude parameter are assigned from Bits<5:0> of the
ASF register. The resulting 14-bit word scales the amplitude from 0 to 1 2
14
.
The MSB of the data-word phase aligns with the MSB of the 16-bit phase parameter of
the DDS. The 8 LSBs of the DDS phase parameter are assigned from Bits<7:0> of the POW
register. The resulting 16-bit word offsets the phase from 0 to 2
π
(1 2
16
) radians.
D<7:0>
8-bit phase (unsigned
integer)
Transmit Enable (TxENABLE)
The AD9910 also accepts a user generated signal applied to the
TxENABLE pin that acts as a gate for the user supplied data. By
default, TxENABLE is considered true for Logic 1 and false for
Logic 0. However, the logical behavior of this pin can be reversed
using the TxENABLE invert bit. When TxENABLE is true, the
device latches data into the device on the expected edge of PDCLK
(based on the PDCLK invert bit). When TxENABLE is false,
even though the PDCLK may continue to operate, the device
ignores the data supplied to the port. Furthermore, when the
TxENABLE pin is held false, then the device internally clears
the 18-bit data-words, or it retains the last value present on the
data port prior to TxENABLE switching to the false state (based
on the setting of the data assembler hold last value bit).
Alternatively, instead of operating the TxENABLE pin as a gate,
it can be driven with a clock signal operating at the parallel port
data rate. When driven by a clock signal, the transition from the
false to true state must meet the required setup and hold time
on each cycle to ensure proper operation. The TxENABLE and
PDCLK timing is shown in Figure 26.
0
FALSE
TRUE
TxENABLE
(BURST)
TxENABLE
(CLOCK)
WORD1
WORD2
WORD3
WORD4WORDN–4
WORDN
PDCLK
PARALLEL
DATA PORT
t
DS
t
DS
t
DH
t
DH
Figure 26. PDCLK and TxENABLE Timing Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| AD9910BSVZ | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9910BSVZ-REEL | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9912 | 1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9913 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ1 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9910BSVZ | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
發布緊急采購，3分鐘左右您將得到回復。