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參數(shù)資料
型號: AD9910BSVZ
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer
中文描述: SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100
封裝: ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁數(shù): 18/60頁
文件大小: 764K
代理商: AD9910BSVZ
AD9910
DIGITAL RAMP MODULATION MODE
In digital ramp modulation mode (Figure 24), the modulated
DDS signal control parameter is supplied directly from the
digital ramp generator (DRG). The ramp generation parameters
are controlled through the serial I/O port.
Rev. 0 | Page 18 of 60
The ramp generation parameters allow the user to control both
the rising and falling slopes of the ramp. The upper and lower
boundaries of the ramp, the step size and step rate of the rising
portion of the ramp, and the step size and step rate of the falling
portion of the ramp are all programmable.
The ramp is digitally generated with 32-bit output resolution.
The 32-bit output of the DRG can be programmed to represent
frequency, phase, or amplitude. When programmed to represent
frequency, all 32 bits are used. However, when programmed to
represent phase or amplitude, only the 16 MSBs or 14 MSBs,
respectively, are used.
The ramp direction (rising or falling) is externally controlled by
the DRCTL pin. An additional pin (DRHOLD) allows the user
to suspend the ramp generator in its present state.
0
16
PARALLEL
INPUT
PDCLK
SCLK
SDIO
I/O_RESET
PROFILE
I/O_UPDATE
RAM
POWER
DOWN
CONTROL
E
DAC_RSET
IOUT
IOUT
CS
TxENABLE
DAC FSC
OSK
A
θ
INVERSE
SINC
FILTER
CLOCK
AMPLITUDE (A)
FREQUENCY (
ω
)
PHASE (
θ
)
DIGITAL
RAMP
GENERATOR
8
DAC FSC
8
2
2
MULTICHIP
SYNCHRONIZATION
SYSCLK
PLL
÷2
C
REF_CLK
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND
CONTROL
S
2
AD9910
PROGRAMMING
REGISTERS
OUTPUT
SHIFT
KEYING
DATA
ROUTE
AND
PARTITION
CONTROL
3
INTERNAL CLOCK TIMING
AND CONTROL
ω
Acos (
ω
t+
θ
)
Asin (
ω
t+
θ
)
S
S
S
P
P
M
2
2
DDS
AUX
DAC
8-BIT
DAC
14-BIT
RAM_SWP_OVR
DRCTL
DRHOLD
DROVER
S
Figure 24. Digital Ramp Modulation Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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