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參數(shù)資料
| 型號： | AD9910BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 58/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ |
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AD9910
Multichip Sync Register
Address 0x0A, 4 bytes are assigned to this register.
Rev. 0 | Page 58 of 60
Table 25. Multichip Sync Register
Bit(s)
31:28
Descriptor
Sync Validation Delay
Explanation
This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the
delayed sync-in signal for the sync validation block in the sync receiver. Default is 0000
2
.
0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 000000
2
.
This 5-bit number sets the output delay (in ~150 ps increments) of the sync generator.
Default is 00000
2
.
This 5-bit number sets the input delay (in ~150 ps increments) of the sync receiver. Default
is 00000
2
.
27
26
25
24
23:18
Sync Receiver Enable
Sync Generator Enable
Sync Generator Polarity
Not Available
Sync State Preset Value
17:16
15:11
Not Available
Output Sync Generator
Delay
Not Available
Input Sync Receiver Delay
10:8
7:3
2:0
Digital Ramp Limit Register
Address 0x0B, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Not Available
Table 26. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
Descriptor
63:32
Digital Ramp Upper Limit
31:0
Digital Ramp Lower Limit
Digital Ramp Step Size Register
Address 0x0C, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 27. Bit Descriptions for Digital Ramp Step Size Register
Bit(s)
Descriptor
Explanation
63:32
Digital Ramp Decrement
Step Size
31:0
Digital Ramp Increment
Step Size
Digital Ramp Rate Register
Address 0x0D, 4 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 28. Bit Descriptions for Digital Ramp Rate Register
Bit(s)
Descriptor
Explanation
31:16
Digital Ramp Negative
Slope Rate
values.
15:0
Digital Ramp Positive Slope
Rate
values.
Explanation
32-bit digital ramp upper limit value.
32-bit digital ramp lower limit value.
32-bit digital ramp decrement step size value.
32-bit digital ramp increment step size value.
16-bit digital ramp negative slope value that defines the time interval between decrement
16-bit digital ramp positive slope value that defines the time interval between increment
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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