- 您現在的位置：買賣IC網 > PDF目錄373970 > AD9910BSVZ (ANALOG DEVICES INC) 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer PDF資料下載
參數資料
| 型號： | AD9910BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 24/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
AD9910
Rev. 0 | Page 24 of 60
REF_CLK
REF_CLK
PLL
VCO
SELECT
DIVIDE
CHARGE
PUMP
OUT
IN
PLL_LOOP_FILTER
ENABLE
PLL_LOOP_FILTER
DRV0
CFR3
<31:30>
2
REFCLK_OUT
XTAL_SEL
REFCLK
INPUT
SELECT
LOGIC
SYSCLK
I
CFR3
<21:19>
N
CFR3
<7:1>
VCO
CFR3
<26:24>
÷2
INPUT DIVIDER BYPASS
CFR3<15>
PLL ENABLE
CFR3
<8>
INPUT DIVIDER
RESETB
CFR3<14>
Figure 30. REF_CLK Block Diagram
94
95
2
90
91
0
1
0
1
2
7
3
0
1
0
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected, the
REF_CLK pins must be driven by an external signal source
(single-ended or differential). Input frequencies up to 2 GHz are
supported. For input frequencies greater than 1 GHz, the input
divider must be enabled for proper operation of the device.
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected, because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT
buffer is controlled by two bits as listed in Table 7.
Table 7. REFCLK_OUT Buffer Control
CFR3<31:30>
REFCLK_OUT Buffer
00
Disabled (tristate)
01
Low output current
10
Medium output current
11
High output current
Crystal Driven REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 31 shows
the recommended circuit configuration.
0
REF_CLK
REF_CLK
39pF
39pF
XTAL
90
91
Figure 31. Crystal Connection Diagram
Direct Driven REF_CLK
When driving the REF_CLK inputs directly from a signal
source either single-ended or differential signals can be used.
With a differential signal source, the REF_CLK pins are driven
with complementary signals and ac-coupled with 0.1 μF
capacitors. With a single-ended signal source, either a single-
ended to differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 μF capacitors are used to ac couple both REF_CLK
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 32 for more details.
The REF_CLK input resistance is ~2.5 kΩ differential (~1.2 kΩ
single-ended). Most signal sources have relatively low output
impedances. The REF_CLK input resistance is relatively high,
therefore, its effect on the termination impedance is negligible
and can usually be chosen to be the same as the output
impedance of the signal source. The bottom two examples in
Figure 32 assume a signal source with a 50 Ω output impedance.
0
TERMINATION
REF_CLK
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT.
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT.
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT.
90
91
0.1μF
0.1μF
PECL,
LVPECL,
OR
LVDS
DRIVER
REF_CLK
90
91
50
0.1μF
0.1μF
BALUN
(1:1)
REF_CLK
REF_CLK
REF_CLK
REF_CLK
90
91
0.1μF
0.1μF
50
Figure 32. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier
An internal phase-locked loop (PLL) provides users of the
AD9910 the option to use a reference clock frequency that is
significantly lower than the system clock frequency. The PLL
supports a wide range of programmable frequency multiplica-
tion factors (12× to 127×) as well as a programmable charge
pump current and external loop filter components (connected
via the PLL_LOOP_FILTER pin). These features add an extra
layer of flexibility to the PLL, allowing optimization of phase
noise performance and flexibility in frequency plan develop-
ment. The PLL is also equipped with a PLL_LOCK pin.
The PLL output frequency range (f
SYSCLK
) is constrained to the
range of 420 MHz ≤ f
SYSCLK
≤ 1 GHz by the internal VCO. In
addition, the user must program the VCO to one of six operating
相關PDF資料 |
PDF描述 |
|---|---|
| AD9910BSVZ-REEL | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| AD9912 | 1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9913 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ1 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
| AD9913BCPZ-REEL71 | Low Power 250 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
發布緊急采購，3分鐘左右您將得到回復。