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參數資料
| 型號： | AD9910BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 中文描述： | SERIAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PDSO100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數： | 37/60頁 |
| 文件大小： | 764K |
| 代理商： | AD9910BSVZ |
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AD9910
Rev. 0 | Page 37 of 60
WAVEFORM START
ADDRESS 0
WAVEFORM END
ADDRESS 0
WAVEFORM START
ADDRESS 1
WAVEFORM END
ADDRESS 1
0
1
RAM_SWP_OVER
RAM PROFILE
RAM
ADDRESS
I/O_UPDATE
0
1
0
0
2
1
1
2
3
4
5
6
7
8
9
10
11
Δ
t
0
Δ
t
1
1
Figure 45. Internal Profile Control Timing Diagram (Continuous)
Internal Profile Control Continuous Waveform
Timing Diagram
An example of an internal profile control, continuous waveform
timing diagram is shown in Figure 45. The diagram assumes
that Internal Profile Control<20:17> is programmed as 1000. It
also assumes that the start address in RAM Profile 1 is greater
than the end address in RAM Profile 0.
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events.
Event 1—An I/O update registers the fact that internal profile
control bits (in Control Function Register 1) are programmed
to 1000. The RAM_SWP_OVR pin is set to Logic 0. The state
machine is initialized to the waveform start address of RAM
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt
0
(as specified by the address
step rate for RAM Profile 0).
Event 2—The state machine reaches the waveform end address
of RAM Profile 0 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt
1
.
Event 4—The state machine reaches the waveform end address
of RAM Profile 1 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to jump back to RAM Profile 0. The state
machine initializes to the waveform start address of RAM
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt
0
.
Event 6 and Event 8—Same as Event 2 and Event 4, respectively.
Event 5 to Event 8—Repeat indefinitely until the internal profile
control bits are reprogrammed and an I/O update is asserted.
RAM Bidirectional Ramp Mode
In bidirectional ramp mode, upon assertion of an I/O update,
the RAM begins operating as a waveform generator using the
parameters programmed only into RAM Profile 0 (unlike ramp
up mode, which uses all eight profiles). Data is extracted from
RAM over the specified address range and at the specified rate
contained in the waveform start address, waveform end address,
and address ramp rate values of the selected RAM profile. The
data is delivered to the specified DDS signal control
parameter(s) based on the RAM playback destination bits.
The PROFILE<2:1> pins are ignored by the internal logic in
this mode. When a RAM profile programmed to operate in this
mode is selected, no other RAM profiles can be selected until
the active RAM profile is reprogrammed with a different RAM
operating mode. The no-dwell high bit is ignored in this mode.
With the bidirectional ramp mode activated via an I/O update
or profile change, the internal state machine readies to extract
data from the RAM at the waveform start address. Data
extraction begins when PROFILE0 is Logic 1, which instructs
the state machine to begin incrementing through the address
range. As long as the PROFILE0 pin remains Logic 1, the state
machine continues to extract data until it reaches the waveform
end address. At this point, the state machine halts until the
PROFILE0 pin is Logic 0 instructing the state machine to begin
decrementing through the address range. As long as the
PROFILE0 pin is Logic 0, the state machine continues to extract
data until it reaches the waveform start address. At this point,
the state machine halts until the PROFILE0 pin is Logic 1.
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相關代理商/技術參數 |
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| AD9910BSVZ | 制造商:Analog Devices 功能描述:IC DDS 1GHZ TQFP-100 制造商:Analog Devices 功能描述:IC, DDS, 1GHZ, TQFP-100 |
| AD9910BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT PAR 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9911 | 制造商:AD 制造商全稱:Analog Devices 功能描述:500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911/PCB | 制造商:Analog Devices 功能描述:500 MSPS DIRECT DGTL SYNTHESIZER W/ 10-BIT DAC AD9911/PCB - Bulk |
| AD9911/PCBZ | 功能描述:BOARD EVAL FOR AD9911 RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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