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參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 15/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9992
features on-chip output drivers for the RG, HL, and H1 to H8
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG current can be adjusted
for optimum rise/fall time for a particular load by using the
drive strength control registers (Addresses 0x35 and 0x36).
The 3-bit drive setting for each output is adjustable in 4.3 mA
increments: 0 = three-state; 1 = 4.3 mA; 2 = 8.6 mA; 3 =
12.9 mA; and 4, 5, 6, 7 = 17.2 mA.
Rev. 0 | Page 15 of 92
As shown in Figure 15, when HCLK Mode 1 is used, the H2,
H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7
outputs, respectively. Using the HCLKMODE register (Address
0x23, Bits [9:7]), it is possible to select a different configuration.
Table 8 shows a comparison of the different programmable
settings for each HCLK mode. Figure 16 and Figure 17 show the
settings for HCLK Mode 2 and HCLK Mode 3, respectively.
Note that it is recommended that all H1 to H8 outputs on the
AD9992 be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs should
only have the AD9992’s H1, H3, H5, and H7 outputs connected
together to drive the CCD’s H1, and the H2, H4, H6, and H8
outputs connected together to drive the CCD’s H2. Similarly, a
CCD with H1, H2, H3, and H4 inputs should have
H1 and H3 connected to the CCD’s H1.
H2 and H4 connected to the CCD’s H2.
H5 and H7 connected to the CCD’s H3.
H6 and H8 connected to the CCD’s H4.
Table 7. Timing Core Register Parameters for H1, H2, HL, RG, SHP, SHD
Parameter
Length
Range
Polarity
1b
High/low
Positive Edge
6b
0 to 63 edge location
Negative Edge
6b
0 to 63 edge location
Sampling Location
6b
0 to 63 edge location
Drive Strength
3b
0 to 4 current steps
Description
Polarity control for H1, H2, HL, and RG (0 = inversion, 1 = no inversion)
Positive edge location for H1, H2, HL, and RG
Negative edge location for H1, H2, HL, and RG
Sampling location for internal SHP and SHD signals
Drive current for H1 to H8 , HL, and RG outputs (4.3 mA per step)
Table 8. HCLK Modes, Selected by Address 0x23, Bits [9:7]
HCLKMODE
Register Value
Mode 1
001
Mode 2
010
Description
H1 edges are programmable, with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1
H1 edges are programmable, with H3 = H5 = H7 = H1
H2 edges are programmable, with H4 = H6 = H8 = H2
H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1
H5 edges are programmable, with H7 = H5 and H6 = H8 = inverse of H5
Invalid register settings
Mode 3
100
Invalid Selection
000, 011, 101, 110, 111
1
2
4
3
H1 TO H8 PROGRAMMABLE LOCATIONS:
1
H1 RISING EDGE.
2
H1 FALLING EDGE.
3
H2 RISING EDGE.
4
H2 FALLING EDGE.
H2, H4, H6, H8
H1, H3, H5, H7
0
Figure 16. HCLK Mode 2 Operation
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