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參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 42/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gate (VSG) pulses are
used to transfer the pixel charges from the light-sensitive image
area into light-shielded vertical registers. From the light-
shielded vertical registers, the image is clocked out line-by-line
using the vertical transfer pulses (XV signals) in conjunction
with the high speed horizontal clocks. The AD9992 has 24
vertical signals, and each signal can be assigned as a VSG pulse
instead of an XV pulse.
Rev. 0 | Page 42 of 92
Table 18 summarizes the VSG control registers, which are
mostly located in the field registers space (see Table 16). The
VSGSELECT register (Address 0x1C in the fixed address space)
determines which vertical outputs are assigned as VSG pulses.
When a signal is selected to be a VSG pulse, only the starting
polarity and two of the V-pattern toggle positions are used. The
VSGPATSEL register in the sequence registers is used to assign
either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal.
Note that only two of the four V-pattern toggle positions are
available when a vertical signal is selected to be a VSG pulse.
The SGACTLINE1 and SGACTLINE2 registers are used to
select which line in the field is the VSG line. The VSG active
line location is used to reference when the substrate clocking
(SUBCK) signal begins to operate in each field. For more
information, see the Substrate Clock Operation (SUBCK)
section.
Also located in the field registers, the SGMASK register selects
which individual VSG pulses are active in a given field. Therefore,
all SG patterns to be preprogrammed into the V-pattern registers
and the appropriate pulses for the different fields can be enabled
separately.
Table 18. VSG Control Registers (also see Field Registers in Table 16)
Register
Length
Range
24b
High/low
(Located in Fixed
Address Space, 0x1C)
VSGPATSEL
24b
High/low
Description
Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.
[0]: XV1 selection (0 = XV pulse; 1 = VSG pulse).
[1]: XV2 selection.
…
[23]: XV24 selection.
When VSG signal is selected using the VSGSELECT register, VSGPATSEL
selects which V-pattern toggle positions are used. When set to 0, Toggle 1
and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).
[1]: XV2 selection.
…
[23]: XV24 selection.
Set high to mask each individual VSG output.
[0]: XV1 mask.
…
[23]: XV24 mask.
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
VSGSELECT
SGMASK
SGACTLINE1
SGACTLINE2
24b
13b
13b
High/low, each VSG
0 to 8191 line no.
0 to 8191 line no.
VD
HD
VSG PATTERN
4
1
2
3
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1
START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).
2
FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).
3
SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).
4
ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).
0
Figure 50. Vertical Sensor Gate Pulse Placement
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