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參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 41/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than the 13-bit V-pattern
toggle position counter. In general, the 13-bit toggle position
counter can be used with the sweep mode feature to support
very wide pulses; however, multiplier mode can be used to
generate even wider pulses.
Rev. 0 | Page 41 of 92
The start polarity and toggle positions are still used in the same
manner as the standard V-pattern group programming, but
VLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
VTOG 2, VTOG 3, and VTOG 4) of the V-pattern group, the
VLEN is multiplied with the VTOG position to allow very long
pulses to be generated. To calculate the exact toggle position,
which is counted in pixels after the start position, use the
following equation:
Position
Toggle
Mode
Multiplier
VLEN
VTOG
×
=
Because the VTOG register is multiplied by VLEN, the resolution
of the toggle position placement is reduced. If VLEN = 4, the
toggle position precision is reduced to 4-pixel increments
instead of to single-pixel increments.
Table 17 summarizes how the V-pattern group registers are used
in multiplier mode operation. In multiplier mode, the VREP
registers must always be programmed to the same value as the
highest toggle position.
Figure 49 illustrates this operation. The first toggle position is 2,
and the second toggle position is 9. In nonmultiplier mode, this
causes the V-sequence to toggle at Pixel 2 and then at Pixel 9 within
a single HD line. However, in multiplier mode toggle positions are
multiplied by the value of VLEN (in this case, 4); therefore, the first
toggle occurs at Pixel 8, and the second toggle occurs at Pixel 36.
Sweep mode has also been enabled to allow the toggle positions
to cross the HD line boundaries.
Table 17. Multiplier Mode Register Parameters
Register
Length
MULTI
1b
VPOL
1b
VTOG
13b
VLEN
13b
VREP
13b
Range
High/low
High/low
0 to 8191 pixel location
0 to 8191 pixels
0 to 8191 pixel location
Description
High enables multiplier mode.
Starting polarity of V1 to V10 signals in each V-pattern group.
Toggle positions for V1 to V10 signals in each V-pattern group.
Used as multiplier factor for toggle position counter.
VREP_EVEN/VREP_ODD must be set to the same value as the highest VTOG value.
V1 TO V10
HD
VLEN
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
PIXEL
NUMBER
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3
5
5
4
1
2
4
2
0
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1
START POLARITY (STARTPOL = 0).
2
FIRST, SECOND, AND THIRD TOGGLE POSITIONS (VTOG1 = 2, VTOG2 = 9).
3
LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4
TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG × VLEN).
5
IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE.
Figure 49. Example of Multiplier Region for Wide Vertical Pulse Timing
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