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參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 68/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
Rev. 0 | Page 68 of 92
0
1
2
3
4
VD
HD
X
X
X
X
N
N – 1
N – 2
N – 3
N – 4
N – 5
N – 6
N – 7
N – 8
N – 9
N – 10
N – 11
N – 12
N – 13
N – 32
N – 33
N – 34
N – 35
H-RESET
NOTES
(PIXEH-COUNTER
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
0
Figure 77. Toggle Position Inhibited Area—Master Mode
N – 1
N
0
1
2
VD
HD
N – 2
N – 3
N – 4
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
N – 5
N – 6
N – 7
N – 8
N – 9
N – 10
N – 11
N – 12
N – 13
N – 32
N – 33
N – 34
N – 35
X
X
X
X
X
X
NOTES
(PIXEH-COUNTER
H-RESET
0
Figure 78. Toggle Position Inhibited Area—Slave Mode
STANDBY MODE OPERATION
The AD9992 contains three standby modes to optimize the
overall power dissipation in a particular application. Bits [1:0]
of Address 0x00 control the power-down state of the device:
STANDBY [1:0] = 0 = normal operation (full power)
STANDBY [1:0] = 1 = Standby1 mode
STANDBY [1:0] = 2 = Standby2 mode
STANDBY [1:0] = 3 = Standby3 mode (lowest power)
Table 26 summarizes the operation of each power-down mode.
The OUTCONTROL register takes priority over the Standby1
and Standby2 modes in determining the digital output states,
but Standby3 mode takes priority over OUTCONTROL.
Standby3 has the lowest power consumption and even shuts
down the crystal oscillator circuit between CLI and CLO.
Therefore, if CLI and CLO are being used with a crystal to
generate the master clock, this circuit is powered down and
there is no clock signal. When returning from Standby3 mode
to normal operation, the timing core must be reset at least
500 μs after the STANDBY register is written to. This allows
sufficient time for the crystal circuit to settle.
The vertical outputs can also be programmed to hold a specific
value during the Standby3 mode by using Address 0x26. This
register is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage when VH
and VL areas are applied. The polarities for Standby1 mode and
Standby2 mode are also programmable, using Address 0x25.
OUTCONTROL = low also uses the same polarities programmed
for Standby1 and Standby2 modes in Address 0x25. The GPO
polarities are programmable using Address 0x27.
Note that the GPO outputs are High-Z by default at power-up
until Address 0x78 is used to select them as outputs.
CLI FREQUENCY CHANGE
If the input clock CLI is interrupted or changed to a different
frequency, the timing core must be reset for proper operation.
After the CLI clock has settled to the new frequency, or the
previous frequency is resumed, write 0 and then 1 to the
TGCORE_RSTB register (Address 0x14). This guarantees that
the timing core operates properly.
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