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參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 79/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZ |
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AD9992
Rev. 0 | Page 79 of 92
Address
33
34
Data
Bits
[5:0]
[13:8]
[16]
[0]
[1]
Default
Value
0
10
1
0
0
Update
Type
SCK
SCK
Name
RGPOSLOC
RGNEGLOC
RGH2POL
H1HBLKRETIME
H2HBLKRETIME
Description
RG rising edge location.
RG falling edge location.
RG polarity control. 0: inverse of Figure 18, 1: no inversion.
Retime H1, H2, HL HBLK to the internal clock. 0: no retime; 1: retime.
Recommended setting is retime enabled (1). Setting to 1 adds one cycle delay
to programmed HBLK positions.
Enable HBLK for HL output. 0: disable; 1: enable.
Enables wide H-clocks during HBLK interval. Set to 0 to disable.
H1 drive strength. 0: off; 1: 4.3 mA; 2: 8.6 mA; 3: 12.9 mA; 4: 4.3 mA;
5: 8.6 mA; 6: 12.9 mA; 7: 17.2 mA.
H2 drive strength (same range as H1DRV).
H3 drive strength (same range as H1DRV).
H4 drive strength (same range as H1DRV).
HL drive strength (same range as H1DRV).
RG drive strength (same range as H1DRV).
H5 drive strength (same range as H1DRV).
H6 drive strength (same range as H1DRV).
H7 drive strength (same range as H1DRV).
H8 drive strength (same range as H1DRV).
SHD sampling edge location.
SHP sampling edge location.
SHP width (controls input dc restore switch active time).
DOUT phase control, positive edge. Specifies location of DOUT.
DOUT phase control, negative edge. Always set to DOUTPHASEP plus
32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.
DCLK mode. 0: DCLK tracks DOUT; 1: DCLK phase is fixed.
Data output delay (t
OD
) with respect to DCLK rising edge.
0: no delay; 1: ~3 ns; 2: ~6 ns; 3: ~9 ns
Invert DCLK output. 0: no inversion, 1: inversion of DCLK.
Enable H-masking during CP operation.
35
[2]
[3]
[7:4]
[2:0]
0
0
4
1
SCK
HLHBLKRETIME
HL_HBLK_EN
HCLK_WIDTH
H1DRV
36
37
38
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[2:0]
[6:4]
[10:8]
[14:12]
[5:0]
[11:6]
[17:12]
[5:0]
[11:6]
1
1
1
1
1
1
1
1
1
0
20
10
0
20
SCK
SCK
SCK
H2DRV
H3DRV
H4DRV
HLDRV
RGDRV
H5DRV
H6DRV
H7DRV
H8DRV
SHDLOC
SHPLOC
SHPWIDTH
DOUTPHASEP
DOUTPHASEN
[12]
[14:13]
0
0
DCLKMODE
DOUTDELAY
39
[15]
[2:0]
0
7
SCK
DCLKINV
CPHMASK
Table 34. Test Registers—Do Not Access
Address
Data Bits
3E ~ 4F
Default Value
Update
Name
Description
Test registers only. Do not access.
Table 35. Test Registers—Do Not Access
Address
Data Bits
50 ~ 6F
Default Value
Update Type
Name
Description
Test registers only. Do not access.
Table 36. Shutter and GPO Registers
Data
Bits
70
[2:0]
[5:3]
Address
Default
Value
0
0
Update
Type
VD
Name
PRIMARY_ACTION
SECOND_ACTION
Description
Selects action for primary and secondary counters.
0: idle (do nothing) autoreset on VD.
1: activate counter (primary: auto exposure/readout).
2: RapidShot: wrap/repeat counter.
3: ShotTimer: delay start of count.
4: ShotTimer with RapidShot.
5: SLR exposure (manual).
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