- 您現在的位置：買賣IC網 > PDF目錄373973 > AD9992BBCZ (ANALOG DEVICES INC) 12-Bit CCD Signal Processor with Precision Timing Generator PDF資料下載
參數資料
| 型號： | AD9992BBCZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 47/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
AD9992
SHUTTER TIMING CONTROL
The AD9992 supports the generation of electronic shuttering
(SUBCK) and also features flexible general-purpose outputs
(GPO) to control mechanical shuttering, CCD substrate bias
switching, and strobe circuitry. In the following documentation,
the terms sense gate (SG) and vertical sense gate (VSG) are used
interchangeably.
Rev. 0 | Page 47 of 92
SUBSTRATE CLOCK OPERATION (SUBCK)
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9992 supports three types of
electronic shuttering: normal, high precision, and low speed.
Along with the SUBCK pulse placement, the AD9992 can
accommodate different readout configurations to further
suppress the SUBCK pulses during multiple field readouts.
The SUBCK signal is a programmable string of pulses, each
occupying a line following the primary sense gate active line,
SGACTLINE1 (registers are shown in Table 20). The SUBCK
signal has programmable pulse width, line placement, and
number of pulses to accurately control the exposure time.
SUBCK: Normal Operation
By default, the AD9992 operates in the normal SUBCK
configuration, in which the SUBCK signal is pulsing in every
VD field (see Figure 55). The SUBCK pulse occurs once per
line, and the total number of repetitions within the field
determines the length of the exposure time. The SUBCK pulse
polarity and toggle positions within a line are programmable using
the SUBCK_POL and SUBCK_TOG1 registers (see Table 20).
The number of SUBCK pulses per field is programmed in the
SUBCKNUM register (Address 0x75).
As shown in Figure 55, the SUBCK pulses always begin in the
line following the SG-active line, which is specified in the
SGACTLINE registers for each field. The SUBCK_POL,
SUBCK_TOG1, SUBCK_TOG2, SUBCKNUM, and
SUBCKSTARTLINE registers are updated at the start of the line
after the sensor gate line, as described in the Updating New
Register Values section.
SUBCK: High Precision Operation
High precision shuttering is used in the same manner as normal
shuttering but uses an additional register to control the last
SUBCK pulse. In this mode, the SUBCK still pulses once per
line, but the last SUBCK in the field has an additional SUBCK
pulse, whose location is determined by the SUBCKHP_TOG
registers, as shown in Figure 56. Finer resolution of the exposure
time is possible using this mode. Leaving the SUBCKHP_TOG
registers set to its maximum value (0xFFFFFF) disables the last
SUBCK pulse (default setting).
SUBCK: Low Speed Operation
Normal and high precision shutter operations are used when
the exposure time is less than 1 field. For exposure times greater
than 1 field, the low speed (LS) shutter features can be used.
The AD9992 includes a field counter (primary field counter) to
regulate long exposure times. The primary field counter must
be activated (Address 0x70) to serve as the trigger for the LS
operation. The durations of the LS exposure and read are
specified by the SGMASK_NUM and SUBCKMASK_NUM
register (Address 0x74), respectively. As shown in Figure 57,
this mode suppresses the SUBCK and VSG outputs for up to
8192 fields (VD periods).
To activate an LS shutter operation, trigger the start of the
exposure by writing to the PRIMARY_ACTION register bits
according to the desired effect. When the primary counter is
activated, the next VD period becomes the first active period of
the exposure for which the VSG and SUBCK masks are applied.
Optionally, if the SUBCKMASK_SKIP1 register is enabled, the
AD9992 ignores the first VSG and SUBCK masks in the
subsequent fields. This is generally desired so that the exposure
time begins in the field after the exposure operation is initiated.
Figure 57 shows operation with SUBCKMASK_SKIP1 = 1.
If the PRIMARY_ACTION register is used while the
SUBCKMASK_NUM and SGMASK_NUM registers are set to 0,
the behavior of the SUBCK and VSG signals are not different
from the normal shutter or high precision shutter operations.
Therefore, the primary field counter can be used for other tasks
(described in the General-Purpose Outputs (GPOS) section)
without disrupting the normal activity. In addition, there exists
a secondary field counter that has no effect on the SUBCK and
VSG signals. These counters are described in detail in the Field
Counters section.
SUBCK Start Line
By default, the SUBCK pulses begin in the line following
SGACTLINE1. For applications where the SUBCK pulse should
be suppressed for one or more lines following the VSG line, the
SUBCKSTARTLINE register can be programmed. This register
setting delays the start of the SUBCK pulses until the specified
number of lines following SGACTLINE1.
Caution
A value of 1 should not be used in the SUBCKSTARTLINE
register. A value of 0 is used to specify the SUBCK pulses to
begin in the next line after the SG line. A value of 2 is used to
specify the SUBCK pulses to begin two lines after the SG line,
and so on.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9992BBCZRL | 12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9995KCP | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995KCPRL | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| AD9995 | 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator |
| ADA4000-2ARMZ-RL | Low Cost, Precision JFET Input Operational Amplifiers |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態:在售 標準包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
發布緊急采購，3分鐘左右您將得到回復。