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參數(shù)資料
型號(hào)： ADAU1702JSTZ-RL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 21/52頁(yè)
文件大小： 773K
代理商： ADAU1702JSTZ-RL
ADAU1702
CONTROL PORTS
The ADAU1702 can operate in one of three control modes:
I
2
C control
SPI control
Self-boot (no external controller)
Rev. 0 | Page 21 of 52
The ADAU1702 has both a 4-wire SPI control port and a
2-wire I
2
C bus control port. Each can be used to set the RAMs
and registers. When the SELFBOOT pin is low at power-up, the
part defaults to I
2
C mode but can be put into SPI control mode
by pulling the CLATCH/WP pin low three times. When the
SELFBOOT pin is set high at power-up, the ADAU1702 loads
its program, parameters, and register settings from an external
EEPROM on startup.
The control port is capable of full read/write operation for all
addressable memory and registers. Most signal processing
parameters are controlled by writing new values to the param-
eter RAM using the control port. Other functions, such as mute
and input/output mode control, are programmed by writing to
the registers.
All addresses may be accessed in both a single-address mode or
a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
memory or register location within the ADAU1702. This
subaddress must be two bytes because the memory locations
within the ADAU1702 are directly addressable and their sizes
exceed the range of single-byte addressing. All subsequent bytes
(starting with Byte 3) contain the data, such as control port data,
program data, or parameter data. The number of bytes per word
depends on the type of data that is being written. The exact formats
for specific types of writes are shown in Table 22 to Table 31.
The ADAU1702 has several mechanisms for updating signal
processing parameters in real time without causing pops or
clicks. If large blocks of data need to be downloaded, the output
of the DSP core can be halted (using the CR bit in the DSP core
control register (Address 2076)), new data can be loaded, and
then the device can be restarted. This is typically done during
the booting sequence at start-up or when loading a new program
into RAM. In cases where only a few parameters need to be
changed, they can be loaded without halting the program. To
avoid unwanted side effects while loading parameters on the fly, the
SigmaDSP provides the safeload registers. The safeload registers
can be used to buffer a full set of parameters (for example, the
five coefficients of a biquad) and then transfer these parameters
into the active program within one audio frame. The safeload
mode uses internal logic to prevent contention between the
DSP core and the control port.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 14 details these
multiple functions.
Table 14. Control Port Pins and SELFBOOT Pin Functions
Pin
I
2
C Mode
SCL/CCLK
SCL—input
SDA/COUT
SDA—open-collector output
ADDR1/CDATA/WB
ADDR1—input
CLATCH/WP
Unused input—tie to ground or VDD
ADDR0
ADDR0—input
SPI Mode
CCLK—input
COUT—output
CDATA—input
CLATCH—input
ADDR0—input
Self-Boot
SCL—output
SDA—open-collector output
WB—writeback trigger
WP—EEPROM write protect, open-collector output
Unused input—tie to ground or VDD
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