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參數資料
| 型號： | ADAU1702JSTZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 36/52頁 |
| 文件大?。?/td> | 773K |
| 代理商： | ADAU1702JSTZ-RL |
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ADAU1702
2064 TO 2068 (0x0810 TO 0x814)—SAFELOAD DATA REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multichannel virtualizing parameters, or dynamics
processing curves. When controlling a biquad filter, for
example, all of the parameters must be updated at the same
time. Doing so prevents the filter from executing with a mix of
old and new coefficients for one or two audio frames, thus
avoiding temporary instability and transients that may take a
long time to decay. To accomplish this, the ADAU1702 uses
safeload data registers to simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients and, as
previously mentioned, it is desirable to do a complete update in
one transaction.
The first step in performing a safeload operation is writing the
parameter address to one of the safeload address registers (2069
to 2073). The 10-bit data-word to be written is the address in
parameter RAM to which the safeload is being performed. After
this address is written, the 28-bit data-word can be written to
the corresponding safeload data register (2064 to 2068).
The data formats for these writes are detailed in Table 30 and
Table 31. Table 39 shows how each of the five address registers
maps to its corresponding data register.
After the address and data registers are loaded, the initiate
safeload transfer bit in the core control register should be set to
Rev. 0 | Page 36 of 52
initiate the loading into RAM. Each of the five safeload registers
takes one of the 512 core instructions to load into the parameter
RAM. The total program lengths should therefore be limited to
507 cycles (512 minus 5) to ensure that the SigmaDSP core
always has at least five cycles available. The safeload is
guaranteed to occur within one LRCLK period (21 μs for a f
S
of
48 kHz) of the initiate safeload transfer bit being set.
The safeload logic automatically sends data to be loaded into
RAM from only those safeload registers that have been written
to since the last safeload operation. For example, if two
parameters are to be updated in the RAM, only two of the five
safeload registers must be written. When the initiate safeload
transfer bit is asserted, only data from those two registers are
sent to the RAM; the other three registers are not sent to the
RAM and may hold old or invalid data.
Table 39. Safeload Address and Data Register Mapping
Safeload
Register
Address Register
0
2069
1
2070
2
2071
3
2072
4
2073
Safeload
Safeload
Data Register
2064
2065
2066
2067
2068
Table 40.
D31
D15
SD31
SD15
D30
D14
SD30
SD14
D29
D13
SD29
SD13
D28
D12
SD28
SD12
D27
D11
SD27
SD11
D26
D10
SD26
SD10
D25
D9
SD25
SD09
D24
D8
SD24
SD08
D39
D23
D7
SD39
SD23
SD07
D38
D22
D6
SD38
SD22
SD06
D37
D21
D5
SD37
SD21
SD05
D36
D20
D4
SD36
SD20
SD04
D35
D19
D3
SD35
SD19
SD03
D34
D18
D2
SD34
SD18
SD02
D33
D17
D1
SD33
SD17
SD01
D32
D16
D0
SD32
SD16
SD00
Default
0x00
0x0000
0x0000
Table 41.
Bit Name
SD [39:0]
Safeload Data
2069 TO 2073 (0x0815 TO 0x819) SAFELOAD ADDRESS REGISTERS
Description
Data (program, parameters, register contents) to be loaded into the RAMs or registers
Table 42.
D15
0
D14
0
D13
0
D12
0
D11
SA11
D10
SA10
D9
SA09
D8
SA08
D7
SA07
D6
SA06
D5
SA05
D4
SA04
D3
SA03
D2
SA02
D1
SA01
D0
SA00
Default
0x0000
Table 43.
Bit Name
SA [11:0]
Safeload Address
Description
Address of data that is to be loaded into the RAMs or registers
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