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參數資料
| 型號： | ADAU1702JSTZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 25/52頁 |
| 文件大小： | 773K |
| 代理商： | ADAU1702JSTZ-RL |
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ADAU1702
SPI PORT
By default, the ADAU1702 is in I
2
C mode, but can be put into SPI
control mode by pulling CLATCH/WP low three times. The SPI
port uses a 4-wire interface, consisting of CLATCH, CCLK,
CDATA, and COUT signals and is always a slave port. The
CLATCH signal should go low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
CDATA on a low-to-high transition. COUT data is shifted out of
the ADAU1702 on the falling edge of CCLK and should be
clocked into a receiving device, such as a microcontroller, on the
CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal is the serial output data. The COUT
signal remains three-stated until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 18. A timing diagram is shown in Figure 4. All
data should be written MSB first. The ADAU1702 cannot be
taken out of SPI mode without a full reset.
Chip Address R/W
Rev. 0 | Page 25 of 52
The first byte of an SPI transaction includes the 7-bit chip address
and a R/W bit. The chip address is set by the ADDR0 pin. This
allows two ADAU1702s to share a CLATCH signal, yet still operate
independently. When ADDR0 is low, the chip address is 0000000;
when it is high, the address is 0000001 (see Table 17). The LSB
of this first byte determines whether the SPI transaction is a
read (Logic Level 1) or a write (Logic Level 0).
Table 17. ADAU1702 SPI Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
0
0
0
0
Subaddress
The 12-bit subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register. The MSBs of the subaddress
are zero-padded to bring the word to a full 2-byte length.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. During a burst mode write, an initial
subaddress is written followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format for continuous mode operation is shown in Table 23 and
Table 25 in the Read/Write Data Formats section.
A sample timing diagram for a single-write SPI operation to the
parameter RAM is shown in Figure 26. A sample timing diagram
of a single-read SPI operation is shown in Figure 27. The COUT
pin goes from three-state to being driven at the beginning of
Byte 3. In this example, Byte 0 to Byte 2 contain the addresses
and R/W bit and subsequent bytes carry the data.
Bit 4
0
Bit 5
0
Bit 6
ADDR0
Bit 7
R/W
Table 18. Generic Control Word Format
Byte 0
chip_adr [6:0], R/W
1
Continues to end of data.
Byte 1
0000, subadr [11:8]
Byte 2
subadr [7:0]
Byte 3
data
Byte 4
1
data
0
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 26. SPI Write to ADAU1702 Clocking (Single-Write Mode)
0
CLATCH
CCLK
CDATA
COUT
BYTE 0
BYTE 1
HI-Z
DATA
DATA
DATA
HI-Z
Figure 27. SPI Read from ADAU1702 Clocking (Single-Read Mode)
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