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參數資料
| 型號： | ADAU1702JSTZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 38/52頁 |
| 文件大?。?/td> | 773K |
| 代理商： | ADAU1702JSTZ-RL |
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ADAU1702
2076 (0x081C)—DSP CORE CONTROL REGISTER
Rev. 0 | Page 38 of 52
Table 46.
D15
RSVD
D14
RSVD
D13
GD1
D12
GD0
D11
RSVD
D10
RSVD
D9
RSVD
D8
AACW
D7
GPCW
D6
IFCW
D5
IST
D4
ADM
D3
DAM
D2
CR
D1
SR1
D0
SR0
Default
0x0000
Table 47. DSP Core Control Register
Bit Name
GD [1:0]
GPIO Debounce Control
Description
Sets debounce time of multipurpose pins that are set as GPIO inputs.
GD [1:0]
00
01
10
11
Setting this bit allows data to be written directly to the auxiliary ADC data registers (2057 to 2060) from the
control port. When this bit is set, the auxiliary ADC data registers ignores the settings on the multipurpose pins.
Time (ms)
20
40
10
5
AACW
Auxiliary ADC Data
Registers Control Port
Write Mode
GPCW
GPIO Pin Setting Register
Control Port Write Mode
IFCW
Interface Registers
Control Port Write Mode
IST
Initiate Safeload Transfer
When this bit is set, the GPIO pin setting register (2056) can be written to directly from the control port and
this register ignores the input settings on the multipurpose pins.
When this bit is set, data can be written directly to the interface registers (2048 to 2055) from the control port.
In that state, the interface registers are not written from the SigmaDSP program.
Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is automatically cleared when
the operation is complete. There are five safeload register pairs (address/data); only those registers that have
been written since the last safeload event are transferred to the parameter RAM.
This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to
transmit audio signals from the ADCs.
This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be set to 1 to
transmit audio signals from the DACs.
This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass through the SigmaDSP core.
ADM
Mute ADCs
DAM
Mute DACs
CR
Clear Internal
Registers to 0
SR [1:0]
Sample Rate
These bits set the number of DSP instructions for every sample and the sample rate at which the ADAU1702
operates. At the default setting of 1×, there are 512 instructions per audio sample. This setting should be used
with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 256 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 128 instructions per cycle and the converters run at a 192 kHz sample rate.
SR [1:0]
Setting
00
1× (512 instructions)
01
2× (256 instructions)
10
4× (128 instructions)
11
Reserved
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