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參數資料
| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統監控/排序電路 |
| 文件頁數： | 17/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060 |
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PROGRAMMNGADM1060
ADM1060
–
17
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
PR OGR AMMABL E L OGIC BL OC K AR R AY
T he ADM1060 contains a Programmable Logic Block
Array (PLBA). T his block is the logical core of the
device. T he PLBA (and the PDBs- see next section) is
what provides the sequencing function of the ADM1060.
T he assertion of the 9 Programmable Driver Outputs
(PDO) is controlled by the PLBA. T he PLBA comprises
of 9 macrocells, 1 per PDO Channel. T he main
components of the macrocells are 2 Wide AND- OR
gates, as shown in Figure 4. Each AND gate represents a
function (A and B) which can be used independently to
control the assertion of the PDO pin. T here are 21 inputs
to each of these AND gates. T hese are:-
T he logic outputs of all 7 of the Supply Fault Detectors
T he 4 GPI logic inputs
T he Watchdog fault detector (Latched and Pulsed)
T he delayed output of any of the other macrocells (the
output of a macrocell cannot be an input to itself, since
this would result in a non- terminating loop).
All 21 inputs are hardwired to both function A and
function B AND gates. T he user can then select which of
these inputs controls the output. T his is done using 2
control signals, IMK (a masking bit, setting it ignores the
relevant input) and POL (a polarity bit, setting it inverts
the input before it is applied to the AND gate). T he effect
of setting these bits can be seen in figure 4 below. T he
inverting gate shown is an X -OR gate, resulting in the
following truth table:-
POL
INPUT SIGNAL
0
0
0
1
1
0
1
1
X -OR OUT PUT
0
1
1
0
Table 25. Truth Table for PLB Input Inversion
T he last 2 entries in the truth table show, that with the
INVERT bit set, the X -OR output is always the inverse of
the input.
Similarly, the ignore gate shown is an OR gate, resulting
in the following truth table:-
IMK
INPUT SIGNAL
0
0
0
1
1
0
1
1
OR OUT PUT
0
1
1
1
Table 26 Truth Table for PLB Input Masking
It can be seen here that once the IMK bit is set the OR
output is always 1, regardless of the input, thus ignoring
it. Overleaf is a detailed diagram of the 21 inputs and the
registers required to program them. T hose shown are just
for function A of PLB1 but function B and all of the
functions in the other 8 PLB
’
s are programmed exactly the
same way. An Enable register allows the user to use
function A or B or both. T he output of functions A and/
or B is inputted to a Programmable Delay Block (PDB)
where a delay can be programmed on both the rising and
falling edge of an input (see next section). T he output of
this PDB block can be progammed to invert before one or
any of the PDO pins is asserted.
T he control bits for these macrocells are stored locally in
latches which are loaded at power up. T hese latches can
also be updated via the serial interface. T he registers
containing the macrocell control bits, and the function of
each bit are defined in the tables overleaf.
Figure 4. Simplified Programmable Logic Block Macrocell Schematic
SIGNAL INPUTS
IMK ( IGNORE)
POL (INVERT)
ENABLE
FUNCTION A
ENABLE
FUNCTION B
PROGRAMMABLE
DELAY
BLOCK
PLBOUT
INVERT
OUTPUT
2 wide AND gates
(20 inputs)
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