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參數資料
| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統監控/排序電路 |
| 文件頁數： | 4/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060 |
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–4–
REV.PrJ 11/02
ADM1060–SPECIFICATIONS
PRELIMINARY TECHNICAL DATA
NOT E S
1
T hese are target specifications and subject to change.
2
At least one VPn must be >=3.0V if used as supply. VH must be >=4.5V if used as supply.
3
L ogic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4
C alibrated Voltage T hresholds are set at Production.
Parameter
M in
T yp
M ax
Units
T est Conditions/Comments
POWE R SUPPLY ARBIT RAT ION
V D D C AP
2.7
2.7
V
Any VPn>=3.0V
V H >=4.5V
Any VPn=6.0V
VH =14.4V
4.75
4.75
5.1
5.1
V
V
POWE R SUPPLY
Supply Current, I
DD
3
mA
VDDC AP=4.75V, no PDO FET
Drivers on, no loaded PDO pullups
to VDDCAP
VDDC AP=4.75V, all PDO FET
Drivers on (loaded with 1 A), no
PDO pullups to VDDCAP
Max. additional load that can be
drawn from PDO pullups to
V D D C AP
5
mA
Additional current available from VDDCAP
1
mA
SUPPLY FAULT DE T E CT ORS
VH Input
Input Impedance
T hreshold Ranges
Mid Range
Programming Step Size
High Range
Programming Step Size
VPn Inputs
Input Impedance
T hreshold Ranges
Ultra Low Range
Programming Step Size
L ow Range
Programming Step Size
Mid Range
Programming Step Size
VBn Inputs
Input Impedance
52
k
From VH to GND
2
6
V
mV
V
mV
15.6
4.8
14.4
37.6
52
k
From VPn to GND
0.6
1.8
V
mV
V
mV
V
mV
4.7
1
3
7.8
2
6
15.6
190
52
30
k
k
k
From VBn to 2.25V (Internal Ref.)
From VBn to GND (positive mode)
From VBn to GND (negative mode)
T hreshold Ranges
Negative Mode:
Mid Range
Programming Step Size
Positive Mode:
L ow Range
Programming Step Size
Mid Range
Programming Step Size
Absolute Accuracy
Absolute Accuracy-
C alibrated Voltage T hresholds
4
-6
-2
V
mV
15.6
1
3
V
mV
V
mV
%
7.8
2
6
15.6
2.5
1.0
%
T A=0
o
C to 85
o
C, T hreshold
Voltage>0.9V
Bits
T hreshold Programming Resolution
8
Digital Glitch Filter
0
100
s
See figure 3. 8 timeout options
between 0 and 100 s
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V
2
, T
A
= -40
o
C to 85
o
C, unless otherwse noted.)
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