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參數資料
| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統監控/排序電路 |
| 文件頁數： | 39/45頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADM1060 |
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PROGRAMMNGADM1060
ADM1060
–
39
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
If the operation is a write operation, the first data byte
after the slave address is a command byte. T his tells the
slave device what to expect next. It may be an instruc-
tion such as telling the slave device to expect a block
write, or it may simply be a register address that tells
the slave where subsequent data is to be written.
Since data can flow in only one direction as defined by
the R/
W
bit, it is not possible to send a command to a
slave device during a read operation. Before doing a
read operation, it may first be necessary to do a write
operation to tell the slave what sort of read operation to
expect and/or the address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In WRIT E mode, the master
will pull the data line high during the 10th clock pulse
Figure 8a. General SMBus Write Timing Diagram
Figure 8b. General SMBus Read Timing Diagram
Figure 8c. Diagram for Serial Bus Timing
to assert a ST OP condition. In READ mode, the mas-
ter device will release the SDA line during the low
period before the 9th clock pulse, but the slave device
will not pull it low. T his is known as No Acknowledge.
T he master will then take the data line low during the
low period before the 10th clock pulse, then high dur-
ing the 10th clock pulse to assert a ST OP condition.
R/W
0
SCL
SDA
1
0
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SLAVE
START BY
MASTER
FRAME 1
SLAVE
ADDRESS
FRAME 2
COMMAND
CODE
1
9
1
ACK. BY
SLAVE
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
FRAME N
DATA
BYTE
1
9
9
SCL
(CONTINUED
)
SDA
(CONTINUED
)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
SLAVE
FRAME 3
DATA BYTE
1
R/W
0
SCL
SDA
1
0
1
1
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
START BY
MASTER
FRAME 1
SLAVE
ADDRESS
FRAME 2
DATA
BYTE
1
9
1
ACK. BY
SLAVE
9
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK.
STOP
BY
MASTER
FRAME N
DATA
BYTE
1
9
9
SCL
(CONTINUED
)
SDA
(CONTINUED
)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 3
DATA BYTE
1
P
S
S
P
t
HD;ST
A
t
HD;DA
T
t
HIG
H
t
SU;DA
T
t
SU;STA
t
SU;ST
O
t
LO
W
t
R
t
F
t
HD;ST
A
SCL
SDA
t
BUF
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