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| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統(tǒng)監(jiān)控/排序電路 |
| 文件頁數(shù)： | 27/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060 |
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ADM1060 LOGIC
ADM1060
–
27
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
PROGRAMMABLE DE LAY BLOCK
Each output of the PLBA is fed into a separate Program-
mable Delay Block (PDB). T he PDB enables the user to
add a delay to the logic block output before it is applied to
either a PDO or one of the other PLB
’
s (the output of a
PLB can be the input to any of the other PLB
’
s- not it-
self). T he PDB operation is similar to that of the glitch
filter (discussed in the SFD section). T here is an impor-
tant difference between the 2 functions, however. T he
delay on the falling edge of an input to the PDB can be
programmed independently of the rising edge. T his al-
lows the user to program the length of the pulse outputted
from the PDB. T hus, for instance, the width of the pulse
from the Watchdog Fault Detector can be adjusted, or the
user can ensure that a supply supervised by one of the
SFD
’
s is within its UV/OV range for a programmed pe-
riod of time before asserting a PDO. A delay of between
0ms and 500ms can be programmed in the PnPDBT IM
registers. 4 bits each are used to program the rising edge
and falling edge. Once programmed, the PDB operates as
follows. If the user programs a delay on the rising edge
of, say, 200ms, the PDB looks for a rising edge on the
input. Once it sees the edge it starts a timer. If the input
remains high and the timer reaches 200ms, then the PDB
immediately outputs a rising edge. If the input falls low
before the timer has reached 200ms then no edge is out-
putted from the PDB and the timer is reset. Because there
is separate control over the falling edge, if no delay is
programmed on the falling edge, the delay defaults to 0
and a falling edge on the input will immediately appear on
the output. If a falling edge delay is programmed, then
the PDB operates exactly the opposite to the way it does
for a rising edge. Again, if a delay of, say, 200ms is pro-
grammed on the falling edge, the PDB looks for a falling
edge on the input. Once it sees the edge, it again starts a
timer. If the input remains low and the timer reaches
200ms, then the output transitions from high to low. A
valid rising edge must appear at the output before a falling
edge delay can be activated. T he function of the PDB is
illustrated in figure 6 below.
Aside from the extra timing flexibility offered, the pro-
grammable delay also provides a crude form of filtering.
In much the same way as the Glitch Filter operates, an
input must be high (or low) for a programmed period of
time before being seen on the output. T ransients which
are shorter that the programmed timeouts will not appear
on the output. T he bitmap for the register which controls
both the rising and falling edges is shown overleaf:-
Figure 6. Functionality of the Programmable Delay Block (PDB)
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