- 您現在的位置：買賣IC網 > PDF目錄373995 > ADM1060 (Analog Devices, Inc.) DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes PDF資料下載
參數資料
| 型號： | ADM1060 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DIP Socket; No. of Contacts:56; Pitch Spacing:0.07"; Row Spacing:0.6"; Terminal Type:PC Board; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):No RoHS Compliant: Yes |
| 中文描述： | 通信系統監控/排序電路 |
| 文件頁數： | 36/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
ADM1060
PROGRAMMNGADM1060
–
36
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
C ONF IGUR A T ION D OWNL OA D A T POWE R - UP
T he configuration of the ADM1060- the UV/OV thresh-
olds, glitch filter timeouts, PL B combinations, PDO pull-
ups etc, is dictated by the contents of the RAM. T he
RAM is comprised of local latches which set the configu-
ration. T hese latches are double buffered and are actually
comprised of 2 identical latches (Latch A and Latch B).
An update of the double- buffered latch updates Latch A
first then Latch B. T he advantage of this architecture is
explained below. T hese latches are volatile memory and
lose their contents at power- down. T herefore, at power-
up the configuration in the RAM must be restored. T his
is achieved by downoading the contents of the EEPROM
(non- volatile memory) to the local latches. T his down-
load occurs in a number of steps.
1. With no power applied to the device, the PDO
’
s are all
high impedance.
2. Once 1V appears on any of the inputs connected to the
VDD Arbitrator (VH or VPn), the PDO
’
s are all (weakly)
pulled to GND.
3. Once the supply rises above the Undervoltage Lockout
of the device (UVLO is 2.5V), the EEPROM starts to
download to the RAM.
4. T he EEPROM downloads its contents to all Latch A
’
s.
5. Once the contents of the EEPROM are completely
downloaded, the device controller outputs a control pulse
enabling all Latch A
’
s to download to all Latch B
’
s, thus
completing the configuration download. Any attempt to
communicate with the device prior to this download
completion will result in a NACK being issued from the
AD M 1060.
UPD A T ING T H E C ONF IGUR A T ION OF T H E
A D M1060
Once powered up, with all of the configuration settings
loaded from EEPROM into the RAM registers, the user
may wish to alter the configuration of functions on the
ADM1060 (eg) change the UV or OV limit of an SFD,
change the fault output of an SFD, change the timeout of
the Watchdog Detector, change the rise time delay of one
of the PDO
’
s etc.
T he ADM1060 provides a number of options which allow
the user to update the configuration differently over the
SMBus interface. All of these options are controlled in
the register UPDCFG. T he options are:-
1. Update the configuration in real time. T he user writes
to RAM across the SMBus and the configuration is up-
dated immediately.
2. Update A Latches
“
offline
”
and then update all B
Latches at the same time. With this method, the configu-
ration of the ADM1060 will remain unchanged and con-
tinue to operate in the original setup until the instruction
is given to update the B Latches.
3. Change EEPROM register contents
“
offline
”
and then
download the revised EEPROM contents to the RAM
registers. Again, with this method, the configuration of the
ADM1060 will remain unchanged and continue to operate
in the original setup until the instruction is given to
change.
T he instruction to download from the EEPROM in option
3 above is also a useful way to restore the original
EEPROM contents if revisions to the configuration are
unsatisfactory to the user and they wish the ADM1060 to
return to a known operating mode.
T his type of operation is possible because of the topology
of the ADM1060. T he Local (volatile) registers, or RAM,
are all double buffered latches. Setting bit 0 of the
UPDCFG register to 1 leaves the double buffered latches
open at all times. If bit 0 is set to 0, then when RAM
write occurs across the SMBus only the first side of the
double buffered latch is written to. T he user must then
write a 1 to bit 1 of the UPDCFG register. T his gener-
ates a pulse to update all of the second latches at once.
Similarly with EEPROM writes.
A final bit in this register is used to enable EEPROM
page erasure. If this bit is set high, then the contents of an
EEPROM page can all be set to 0. If low, then the con-
tents of a page cannot be erased, even if the command
code for page erasure is programmed across the SMBus.
T he bitmap for register UPDCFG is shown below. A
flow chart for download at power up and subsequent con-
figuration updates is shown overleaf:-
相關PDF資料 |
PDF描述 |
|---|---|
| ADM1060ARU | CON-HDR64POS2ROW 4WALL.1X.1SP,RTANG,LOPF |
| ADM1064 | Super Sequencer with Voltage Readback ADC |
| ADM1064ACP | Super Sequencer with Voltage Readback ADC |
| ADM1064ACP-REEL | Super Sequencer with Voltage Readback ADC |
| ADM1064ACP-REEL7 | Super Sequencer with Voltage Readback ADC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADM1060ARU | 功能描述:IC SUPERVIS/SEQUENC 7-CH 28TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監控器 系列:Super Sequencer® 標準包裝:1 系列:- 類型:簡單復位/加電復位 監視電壓數目:1 輸出:開路漏極或開路集電極 復位:高有效 復位超時:- 電壓 - 閥值:1.8V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:6-TSOP（0.059"，1.50mm 寬）5 引線 供應商設備封裝:5-TSOP 包裝:剪切帶 (CT) 其它名稱:NCP301HSN18T1GOSCT |
| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| ADM1060ARUCS0100R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| ADM1060ARUCS0101R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
| ADM1060ARUCS0102R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
發布緊急采購，3分鐘左右您將得到回復。