
ADM1060
–6–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
Pin
Mnemonic
F unction
1
A0
Logic input. Controls the 7th bit (LSB) of the 7 bit Serial Bus Address.
2
A1
Logic input. Controls the 6th bit of the 7 bit Serial Bus Address.
3
SD A
Serial Bus data I/O pin. Open- Drain output. Requires 2.2k pullup resistor
4
SC L
Open- Drain Serial Bus Clock pin. Requires 2.2k pullup resistor
5
V D D C AP
V
DD
bypass capacitor pin. A capacitor from this pin to GND stabilises the V
DD
Arbitrator.
0.1 F is recommended for this function.
6
G N D
Ground. Connect to common of power supplies.
7
V C C P
Reservoir Capacitor for Central Charge Pump. T his charge pump powers all of the internal
circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce
12V of gate drive on PDO
’
s 1- 4.
8
V H
High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between
4.8V and 14.4V can be applied to this pin. T he V
DD
arbitrator will select this supply to power
the ADM1060 if it is the highest supply supervised.
9-12
VP1-4
Positive Only Supply Inputs. 2 input ranges. A supply of between 1V and 3V or between
2V and 6V can be applied to this pin. T he V
DD
arbitrator will select one of these supplies to
power the ADM1060 if it is the highest supply supervised.
13-14
V B1-2
Bipolar Supply Inputs. 2 modes. 2 input ranges in positive mode. 1 input range in negative
mode. A supply of between -6V and -2V can be applied to this pin when set in negative mode.
A supply of between 1V and 3V or between 2V and 6V can be applied to this pin when set in
positive mode.
15-23
PD O_1-9
Programmable Driver Output pin. All 9 can be programmed as logic outputs with multiple
pull-up options to VDD or VPn. PDO
’
s 1 to 4 can also provide a charge-pump generated
gate drive for external N- Channel FET
24
W D I
Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock
fails to transition from low-to-high or high-to-low within a programmed timeout period (up to
18sec).
25-28
Reset,
G PI_4-1
General Purpose Logic Input. T T L compatible Logic. Can be used as, say, a
a Chip Enable pin or as an input for a control logic signal which may be critical to the power
up/down sequence of the supplies under control.
Manual
ADM1060 PIN CONFIGURATION
A BSOL UT E MA X IMUM R A T INGS*
Voltage on VH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Voltage on VP
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on VB
Pins . . . . . . . . . . . . . . . . . . . . . -7 V to +7V
Voltage on A0,A1 . . . . . . . . . . . . . . -0.3V to (V
C C
+0.3V)
Voltage on Any Other Input . . . . . . . . . . . . . . -0.3V to 6.5V
Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . ±5mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . ±20mA
Maximum Junction T emperature (T
J
max) . . . . . . .150
°
C
Storage T emperature Range . . . . . . . . .
–
65
°
C to +150
°
C
L ead T emperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . +215
°
C
ESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under
“
Absolute Maximum Ratings
”
may
cause permanent damage to the device. T his is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. E xposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
T H E R MA L C H A R A C T E R IST IC S
28-Pin T SSOP Package:
JA
= 98
°
C/Watt
ORDE RING GUIDE
Temperature
Range
Package
Description
Package
Option
Model
ADM1060ARU
-40
°
C to +85
°
C
28-PinT SSOP
RU-28
2
3
5
6
7
9
10
11
12
13
14
1
ADM1060
GPI1
GPI2
GPI3
GPI4
WDI
GND
VDDCAP
27
26
25
24
23
22
21
20
18
17
16
15
28
VH
VP1
VP2
VP3
VB1
PDO8
PDO6
PDO5
SCL
SDA
A1
A0
VCCP
PDO1
PDO2
VP4
VB2
PDO3
PDO4
DRAFT
PINOUT
P IN F UNC T ION D E SC R IP T ION