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參數資料
| 型號： | ADM1060ARU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 電源管理 |
| 英文描述： | CON-HDR64POS2ROW 4WALL.1X.1SP,RTANG,LOPF |
| 中文描述： | 7-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數： | 38/45頁 |
| 文件大小： | 303K |
| 代理商： | ADM1060ARU |
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ADM1060
PROGRAMMNGADM1060
–
38
–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DATA
INT E RNAL RE GIST E RS OF T HE AD M1060
T he ADM1060 contains a large number of data registers.
A brief description of the principal registers is given be-
low. More detailed descriptions are given in the relevant
sections of the data sheet.
Address Pointer Register:
T his register contains the address
that selects one of the other internal registers. When writing to
the ADM1060, the first byte of data is always a register ad-
dress, which is written to the Address Pointer Register.
Configuration Registers:
Provide control and configuration
for various operating parameters of the ADM1060.
Polarity Registers:
T hese registers define the polarity of
inputs to the PLBA
Mask Registers:
Allow masking of individual inputs to the
PLBA and also masking of faults in the fault reporting
registers.
E E P R O M
T he ADM1060 has 512 bytes of non-volatile, Electrically-
Erasable Programmable Read-Only Memory (EEPROM),
from register addresses F800h to F9FFh. T his may be
used for permanent storage of data that will not be lost
when the ADM1060 is powered down, unlike the data in
the volatile registers. Although referred to as Read Only
Memory, the EEPROM can be written to (as well as read
from) via the serial bus in exactly the same way as the
other registers. T he only major differences between the
E
2
PROM and other registers are:
1. An EEPROM location must be blank before it can be
written to. If it contains data, it must first be erased.
2. Writing to EEPROM is slower than writing to RAM.
3. Writing to the EEPROM should be restricted because
it has a limited write/cycle life of typically 10,000 write
operations, due to the usual EEPROM wear-out
mechanisms.
T he EEPROM is split into 16 (0 to 15) pages of 32 Bytes
each. Pages 0 to 6, starting at address F800, hold the
configuration data for the applications on the ADM1060
(the PLB, SFD
’
s, GPI
’
s, WDI, PDO
’
s etc.). T hese
EEPROM addresses are the same as the RAM register
addresses, prefixed by F8. Page 7 is reserved. Pages 8 to
15 are for customer use. Data can be downloaded from
EEPROM to RAM in one of 2 ways:-
1. At Power- up, pages 0 to 6 are downloaded.
2. Setting bit 2 of the UPDCFG Register (90h) performs
a user download of pages 0 to 6.
SE R IAL BUS INT E R F AC E
Control of the ADM1060 is carried out via the serial Sys-
tem Management Bus (SMBus). T he ADM1060 is con-
nected to this bus as a slave device, under the control of a
master device. It takes approximately 2ms after power up
for the ADM1060 to download from it's EEPROM.
T herefore access is restricted to the ADM1060 until the
download is completed.
ID E NT IF Y ING T HE AD M1060 ON T HE SMBUS
T he ADM1060 has a 7-bit serial bus slave address. When
the device is powered up, it will do so with a default serial
bus address. T he five MSB's of the address are set to
10101, the two LSB's are determined by the logical states
of pin A1 and A0. T his allows the connection of 4
ADM1060
’
s to the one SMBus. T he device also has a
number of identification registers (read only) which can be
read across the SMBus. T hese are:-
Name
Address
Value
MANID 93h
41h
F unction
Manufacturer ID for
Analog Devices
Device ID
Silicon Revision
S/w brand
S/w brand
D E V ID 94h
RE V ID 95h
MARK 1 96h
MARK 2 97h
3E h
--h
--h
--h
GE NE R AL SMBUS T IMING
Figures 8a and 8b show timing diagrams for general read
and write operations using the SMBus. T he SMBus speci-
fication defines specific conditions for different types of
read and write operation, which are discussed later.
T he general SMBus protocol operates as follows:
1. T he master initiates data transfer by establishing a
ST ART condition, defined as a high to low transition
on the serial data line SDA whilst the serial clock line
SCL remains high. T his indicates that a data stream
will follow. All slave peripherals connected to the serial
bus respond to the ST ART condition, and shift in the
next 8 bits, consisting of a 7-bit slave address (MSB
first) plus a R/
W
bit, which determines the direction of
the data transfer, i.e. whether data will be written to or
read from the slave device (0 = write, 1 = read).
T he peripheral whose address corresponds to the trans-
mitted address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the Acknowledge Bit, and holding it low dur-
ing the high period of this clock pulse. All other de-
vices on the bus now remain idle whilst the selected
device waits for data to be read from or written to it. If
the R/
W
bit is a 0 then the master will write to the slave
device. If the R/
W
bit is a 1 the master will read from
the slave device.
2. Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an Acknowledge Bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal
and remain stable during the high period, as a low to
high transition when the clock is high may be inter-
preted as a ST OP signal.
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| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件狀態:上次購買時間 標準包裝:1 |
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