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參數資料
| 型號： | ADSP-21MSP58BST-104 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputers |
| 中文描述： | 24-BIT, 13 MHz, OTHER DSP, PQFP100 |
| 封裝： | METRIC, PLASTIC, TQFP-100 |
| 文件頁數： | 10/40頁 |
| 文件大?。?/td> | 372K |
| 代理商： | ADSP-21MSP58BST-104 |
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REV. 0
–10–
ADSP-21msp58/59
A signed ROM Verification Form and a purchase order for pro-
duction units are required prior to any product being manufac-
tured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for pro-
duction units. An invoice against your purchase order for the
NRE charges is issued at this time.
T here is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for de-
tails. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
ANALOG INT E RFACE
T he analog interface contains encoding circuitry (ADC), decod-
ing circuitry (DAC), and processor interface logic. A block dia-
gram of the ADSP-21msp58/59 analog section is shown in
Figure 8.
T he analog interface is configured through the Analog Control
Register and the Analog Autobuffer/Powerdown Register (refer
to “ADSP-21msp58/59 Registers”). T he Analog Control Regis-
ter DM[0x3FEE] configures the programmable gain stages, the
analog input multiplexer, and the analog interface powerdown
state. Note that the unused bits must be cleared to zero.
16
OUTPUT
DIFFERENTIAL AMP
VIN
NORM
VIN
AUX
DECOUPLE
REF_FILTER
V
REF
VOUT
P
VOUT
N
MUX
DAC
PGA
ANALOG
SMOOTHING
FILTER
BUF
VOLTAGE
REFERENCE
ADC
PGA
16-BIT
SIGMA-
DELTA
DAC
16-BIT
SIGMA-
DELTA
ADC
PROCESSOR
INTERFACE
Figure 8. Analog Interface Block Diagram
A/D Conversion
T he A/D conversion circuitry of the analog interface consists of
an analog multiplexer, a programmable gain amplifier (ADC
PGA), and a 16-bit sigma-delta analog-to-digital converter
(ADC).
Analog Input Multiplexer and Amplifiers
T he analog multiplexer selects either the NORM or AUX input
to the ADC’s sigma-delta modulator. T he inputs should be ac
coupled.
T he ADC PGA may be used to additionally increase the signal
level by +6 dB, +20 dB, or +26 dB. T his gain is selected by bit
9 and bit 0 (IG0, IG1) of the analog control register. Input sig-
nal level to the sigma-delta ADC should not exceed the V
INMAX
specification.
Analog-T o-Digital Converter
T he analog interface’s analog-to-digital converter consists of a
4th-order analog sigma-delta modulator, an anti-aliasing deci-
mation filter, and an optional digital high-pass filter. For a detailed
description of the ADC components, refer to the
ADSP-2100
Family User’s Manual
, Chapter 8, “Analog Interface.”
Bit 10 of the Analog Control Register (0x3FEE) may be set to
add an offset to the input of the ADC sigma-delta converter.
T his offset moves ADC sigma-delta idle tones out of the 4.0
kHz speech band range. T his added offset must be removed by
the ADC high-pass filter. T herefore, the high-pass filter must be
inserted when you use the offset feature.
D/A Conversion
T he D/A conversion circuitry of the analog interface consists of
a sigma-delta digital-to-analog converter (DAC), an analog
smoothing filter, a programmable gain amplifier (DAC PGA),
and a differential output amplifier.
Digital-to-Analog Converter
T he digital-to-analog converter consists of an optional digital
high-pass filter, an anti-imaging interpolation filter, and a
sigma-delta modulator. T he digital filters and the sigma-delta
modulator have the same characteristics as the filters and
modulator of the ADC. For detailed description of the DAC
components, refer to the
ADSP-2100 Family User’s Manual
,
Chapter 8, “Analog Interface.”
Analog Smoothing Filter and Programmable Gain Amplifier
T he analog smoothing filter consists of a 3rd-order switched ca-
pacitor filter with a 3 dB point at approximately 25 kHz.
T he DAC’s programmable gain amplifier (DAC PGA) can be
used to adjust the output signal level by –15 dB to +6 dB in
3 dB increments. T his gain is selected by bits 2–4 (OG0, OG1,
OG2) of the analog control register.
Differential Output Amplifier
T he analog output signal (VOUT
P
, VOUT
N
) is produced by a
differential amplifier. T he differential amplifier meets specifica-
tions for loads greater than 2 k
and has a maximum differen-
tial output swing of
±
3.156 V peak-to-peak (3.17 dBm0). T he
DAC will drive loads smaller than 2 k
, but with degraded
performance.
T he output signal is dc-biased to the on-chip voltage reference
(V
REF
) and can be ac-coupled directly to a load or dc-coupled to
an external amplifier.
T he VOUT
P
, VOUT
N
output must be used as a differential sig-
nal otherwise performance will be severely compromised. Do
not use either pin as a single-ended output.
OPE RAT ING T HE ANALOG INT E RFACE
T he analog interface is operated with several memory-mapped
control and data registers. T he ADC and DAC I/O data is re-
ceived and transmitted through two memory-mapped data regis-
ters. T he data can also be autobuffered directly into (or from)
on-chip memory. In both cases, the I/O processing is interrupt
driven; two interrupts are dedicated to the analog interface, one
for the ADC receive data and one for the DAC transmit data.
T he ADSP-21msp58/59 must have an input clock frequency of
13 MHz. At this frequency, analog-to-digital and digital-to-ana-
log converted data is transmitted at an 8 kHz rate with a single
16-bit word transmitted every 125
μ
s.
For detailed information about the analog interface, refer to the
ADSP-2100 Family User’s Manual
, Chapter 8, “Analog Interface.”
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